參數資料
型號: μPD78078Y
廠商: NEC Corp.
元件分類: 8位微控制器
英文描述: 8 Bit Single Chip Microcontrollers
中文描述: 8位單片機微控制器
文件頁數: 49/84頁
文件大小: 625K
代理商: ΜPD78078Y
49
μ
PD78076Y, 78078Y
(b) Except when MCS = 1, PCC2 to PCC0 = 000B (T
A
= –40 to + 85
°
C, V
DD
= 2.7 to 5.5 V)
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
ASTB high-level width
t
ASTH
t
CY
– 80
ns
Address setup time
t
ADS
t
CY
– 80
ns
Address hold time
t
ADH
0.4t
CY
– 10
ns
Data input time from address
t
ADD1
(3 + 2n)t
CY
– 160
ns
t
ADD2
(4 + 2n)t
CY
– 200
ns
Data input time from RD
t
RDD1
(1.4 + 2n)t
CY
– 70
ns
t
RDD2
(2.4 + 2n)t
CY
– 70
ns
Read data hold time
t
RDH
0
ns
RD low-level width
t
RDL1
(1.4 + 2n)t
CY
– 20
ns
t
RDL2
(2.4 + 2n)t
CY
– 20
ns
WAIT
input time from RD
t
RDWT1
t
CY
– 100
ns
t
RDWT2
2t
CY
– 100
ns
WAIT
input time from WR
t
WRWT
2t
CY
– 100
ns
WAIT low-level width
t
WTL
(1 + 2n)t
CY
(2 + 2n)t
CY
ns
Write data setup time
t
WDS
(2.4 + 2n)t
CY
–60
ns
Write data hold time
t
WDH
Load resistance
5 k
20
ns
WR low-level width
t
WRL
(2.4 + 2n)t
CY
– 20
ns
RD
delay time from ASTB
t
ASTRD
0.4t
CY
– 30
ns
WR
delay time from ASTB
t
ASTWR
1.4t
CY
– 30
ns
ASTB
delay time from
RD
at external fetch
t
RDAST
t
CY
–10
t
CY
+ 20
ns
Address hold time from
RD
at external fetch
t
RDADH
t
CY
– 80
t
CY
+ 50
ns
Write data output time from RD
t
RDWD
0.4t
CY
– 30
ns
Write data output time from WR
t
WRWD
0
60
ns
Address hold time from WR
t
WRADH
t
CY
– 60
t
CY
+ 60
ns
RD
delay time from WAIT
t
WTRD
0.6t
CY
+ 180
2.6t
CY
+ 180
ns
WR
delay time from WAIT
t
WTWR
0.6t
CY
+ 120
2.6t
CY
+ 120
ns
Remarks 1.
MCS: Bit 0 of the oscillation mode select register (OSMS)
2.
PCC2 to PCC0: Bits 2 to 0 of the processor clock control register (PCC)
3.
t
CY
= T
CY
/4
4.
n indicates the number of waits.
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