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CHAPTER 2 PIN FUNCTIONS
(3) P20 through P27 (Port 2) ... 3-state I/O
Port 2 is an 8-bit I/O port with an output latch. This port can be set in the input or output mode in 1-bit units by using
port 2 mode register (PM2) (however, P20 is input-only).
In addition to the input/output port function, port 2 also functions as a control signal input pins such as for external
interrupt signals, and to output the timer signal of timer 0 (refer to
Table 2-3
). P21 through P24 serve as the timer
output pins of timer 0 if so specified by port 2 mode control register (PMC2). The level of each pin of this port can
always be read or tested regardless of the multiplexed function. All the eight pins are Schmitt trigger input pins
to prevent malfunctioning due to noise.
When RESET is input, this port is set in the input mode (output high-impedance status), and the contents of the
output latch are undefined.
Table 2-3. Operation Mode of Port 2
(n = 0 to 7)
Mode
Port Mode
Control Signal Output Mode
Set condition
PMC2n = 0
PMC2n = 1
PM2n = 0
PM2n = 1
PM2n =
¥
P20
–
Input port/NMI input
Note
–
P21
Output port
Input port/INTP0 input
TO00 output
P22
Input port/INTP1 input
TO01 output
P23
Input port/INTP2 input
TO02 output
P24
Input port/INTP3 input
TO03 output
P25
Input port/INTP4 input
–
P26
Input port/INTP5 input/TI2 input
P27
Input port/INTP6 input/TI3 input
Note
The NMI input pin accepts an interrupt request regardless of whether interrupts are enabled or disabled.
Remark
¥
: don’t care
(a) Port mode
(i) Function as port pin
Each port pin set in the port mode by the port 2 mode control register (PMC2) can be set in the input or
output mode in 1-bit units by the port 2 mode register (PM2) (however, P20 is fixed in input only).
(ii) Function as control signal input pins
If PMC2n (n = 0 to 7) bit of PMC2 is “0” and if PM2n (n = 0 to 7) bit of PM2 is “1”, the pins of port 2 can
be used as the following control signal input pins.
NMI (Non-maskable Interrupt)
This pin inputs an external non-maskable interrupt request. Whether the interrupt request is detected
at the rising or falling edge can be specified by using external interrupt mode register 0 (INTM0).