
– viii –
LIST OF FIGURES (1/6)
Figure No.
Title
Page
1-1
Comparison of Noise Level between
μ
PD78064B Subseries and Existing Model (
μ
PD78064).....
14
2-1
Pin Input/Output Circuit List ...............................................................................................................
30
3-1
3-2
3-3
3-4
3-5
3-6
3-7
3-8
3-9
3-10
Memory Map (
μ
PD78064B)................................................................................................................
Memory Map (
μ
PD78P064B) .............................................................................................................
Data Memory Addressing (
μ
PD78064B) ...........................................................................................
Data Memory Addressing (
μ
PD78P064B) .........................................................................................
Program Counter Configuration .........................................................................................................
Program Status Word Configuration ..................................................................................................
Stack Pointer Configuration................................................................................................................
Data to be Saved to Stack Memory ...................................................................................................
Data to be Restored from Stack Memory ..........................................................................................
General Register Configuration..........................................................................................................
33
34
37
38
39
39
40
40
41
42
4-1
4-2
4-3
4-4
4-5
4-6
4-7
4-8
4-9
4-10
4-11
4-12
4-13
4-14
4-15
4-16
4-17
Port Types ...........................................................................................................................................
Block Diagram of P00 and P07 ..........................................................................................................
Block Diagram of P01 to P05 .............................................................................................................
Block Diagram of P10 to P17 .............................................................................................................
Block Diagram of P25 and P26 ..........................................................................................................
Block Diagram of P27 .........................................................................................................................
Block Diagram of P30 to P37 .............................................................................................................
Block Diagram of P70 .........................................................................................................................
Block Diagram of P71 and P72 ..........................................................................................................
Block Diagram of P80 to P87 .............................................................................................................
Block Diagram of P90 to P97 .............................................................................................................
Block Diagram of P100 to P103.........................................................................................................
Block Diagram of P110 to P117.........................................................................................................
Block Diagram of Falling Edge Detection Circuit ..............................................................................
Port Mode Register Format ................................................................................................................
Pull-Up Resistor Option Register Format ..........................................................................................
Key Return Mode Register Format ....................................................................................................
57
61
61
62
63
64
65
66
67
68
69
70
71
72
74
75
76
5-1
5-2
5-3
5-4
5-5
5-6
5-7
5-8
5-9
5-10
Block Diagram of Clock Generator ....................................................................................................
Subsystem Clock Feedback Resistor ................................................................................................
Processor Clock Control Register Format .........................................................................................
Oscillation Mode Selection Register Format .....................................................................................
Main System Clock Waveform due to Writing to OSMS...................................................................
External Circuit of Main System Clock Oscillator..............................................................................
External Circuit of Subsystem Clock Oscillator .................................................................................
Examples of Resonator with Bad Connection ...................................................................................
Main System Clock Stop Function .....................................................................................................
System Clock and CPU Clock Switching...........................................................................................
80
81
82
84
84
85
86
86
90
93