
– x –
6-37
6-38
Capture Register Data Retention Timing...........................................................................................
Operation Timing of OVF0 Flag .........................................................................................................
134
135
7-1
7-2
7-3
7-4
7-5
7-6
7-7
7-8
7-9
7-10
7-11
7-12
7-13
7-14
7-15
7-16
8-Bit Timer/Event Counters 1 and 2 Block Diagram .........................................................................
Block Diagram of 8-Bit Timer/Event Counter Output Control Circuit 1 ............................................
Block Diagram of 8-Bit Timer/Event Counter Output Control Circuit 2 ............................................
Timer Clock Select Register 1 Format...............................................................................................
8-Bit Timer Mode Control Register Format .......................................................................................
8-Bit Timer Output Control Register Format......................................................................................
Port Mode Register 3 Format.............................................................................................................
Interval Timer Operation Timings.......................................................................................................
External Event Counter Operation Timings (with Rising Edge Specified) .......................................
Timing of Square Wave Output Operation ........................................................................................
Interval Timer Operation Timing.........................................................................................................
External Event Counter Operation Timings (with Rising Edge Specified) .......................................
Timing of Square Wave Output Operation ........................................................................................
8-Bit Timer Registers 1 and 2 Start Timing .......................................................................................
External Event Counter Operation Timing.........................................................................................
Timing after Compare Register Change during Timer Count Operation..........................................
143
144
144
146
147
148
149
150
153
155
156
158
160
161
161
162
8-1
8-2
8-3
Watch Timer Block Diagram...............................................................................................................
Timer Clock Select Register 2 Format...............................................................................................
Watch Timer Mode Control Register Format.....................................................................................
165
166
167
9-1
9-2
9-3
Watchdog Timer Block Diagram ........................................................................................................
Timer Clock Select Register 2 Format...............................................................................................
Watchdog Timer Mode Register Format............................................................................................
171
173
174
10-1
10-2
10-3
10-4
Remote Controlled Output Application Example ...............................................................................
Clock Output Control Circuit Block Diagram .....................................................................................
Timer Clock Select Register 0 Format...............................................................................................
Port Mode Register 3 Format.............................................................................................................
177
178
180
181
11-1
11-2
11-3
Buzzer Output Control Circuit Block Diagram ...................................................................................
Timer Clock Select Register 2 Format...............................................................................................
Port Mode Register 3 Format.............................................................................................................
183
185
186
12-1
12-2
12-3
12-4
12-5
12-6
A/D Converter Block Diagram ............................................................................................................
A/D Converter Mode Register Format ...............................................................................................
A/D Converter Input Select Register Format.....................................................................................
External Interrupt Mode Register 1 Format .......................................................................................
A/D Converter Basic Operation ..........................................................................................................
Relations between Analog Input Voltage and A/D Conversion Result.............................................
188
191
192
193
195
196
LIST OF FIGURES (3/6)
Figure No.
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