參數(shù)資料
型號(hào): 030_PCI
英文描述: Using a PCI Bus as the I/O Bus on an Am29030 Microprocessor Design
中文描述: 用的I / O上Am29030微處理器設(shè)計(jì)的PCI總線總線
文件頁(yè)數(shù): 14/25頁(yè)
文件大小: 352K
代理商: 030_PCI
AMD
21
Title
ST1 :=
MEM_ACCESS
MEM_RDY.CLKF = MEMCLK
MEM_RDY :=
PROC_BGRT * REQ * /A31 * /A30 * /MEM_RDY
+ MEM_ACCESS * /MEM_RDY
+ PROC_BGRT * MEM_ACCESS * MEM_RDY * BURST
+ /PROC_BGRT * MEM_ACCESS * MEM_RDY * PCI_FRAME
+ /PROC_BGRT * MEM_ACCESS * MEM_RDY * /PCI_FRAME * /PCI_IRDY
; ROM_CS ALSO DRIVES THE RDN PIN OF THE Am29030 PROCESSOR AND NEEDS TO BE 1 IF THE
; ROM IS 8 BITS WIDE AND 0 IF IT 16 BITS WIDE DURING A RESET. SO TO DO THIS,
; RESET WOULD BE OR’D WITH THE ROM_CS EQUATION IF 16-BIT MEMORY IS NEEDED.
; IT IS CURRENTLY COMMENTED OUT.
ROM_CS =
PROC_BGRT * REQ * /A31 * /A30
;
+ RESET
PROC_RDY =
PROC_BGRT * MEM_RDY
+ PROC_BGRT * PCI_DATA_CYCLE * PCI_TRDY * PCI_IRDY
MINIMIZE_OFF
RAS0 =
MEM_ACCESS
+ REF_ACCESS * /MEMCLK
+ RAS0 * REF_ACCESS
MUX =
MEM_ACCESS * /MEMCLK
+ MEM_ACCESS * MUX
CAS0 =
REF_ACCESS
+ MUX * MEM_ACCESS * ST1 * /INTERNAL_WRITE * MEMCLK * DELAY_IN
+ MUX * MEM_ACCESS * ST1 * /INTERNAL_WRITE * CAS0 * DELAY_IN
+ MUX * MEM_ACCESS * ST1 * /INTERNAL_WRITE * CAS0 * /MEMCLK
+ MUX * MEM_ACCESS * ST1 * PROC_BGRT * INTERNAL_WRITE * WE0 * /MEMCLK
+ MUX * MEM_ACCESS * ST1 * /PROC_BGRT * INTERNAL_WRITE * PCI_C_BE0
* /MEMCLK * /ADD_STOP
CAS1 =
REF_ACCESS
+ MUX * MEM_ACCESS * ST1 * /INTERNAL_WRITE * MEMCLK * DELAY_IN
+ MUX * MEM_ACCESS * ST1 * /INTERNAL_WRITE * CAS1 * DELAY_IN
+ MUX * MEM_ACCESS * ST1 * /INTERNAL_WRITE * CAS1 * /MEMCLK
+ MUX * MEM_ACCESS * ST1 * PROC_BGRT * INTERNAL_WRITE * WE1 * /MEMCLK
+ MUX * MEM_ACCESS * ST1 * /PROC_BGRT * INTERNAL_WRITE * PCI_C_BE1
* /MEMCLK * /ADD_STOP
CAS2 =
REF_ACCESS
+ MUX * MEM_ACCESS * ST1 * /INTERNAL_WRITE * MEMCLK * DELAY_IN
+ MUX * MEM_ACCESS * ST1 * /INTERNAL_WRITE * CAS2 * DELAY_IN
+ MUX * MEM_ACCESS * ST1 * /INTERNAL_WRITE * CAS2 * /MEMCLK
+ MUX * MEM_ACCESS * ST1 * PROC_BGRT * INTERNAL_WRITE * WE2 * /MEMCLK
+ MUX * MEM_ACCESS * ST1 * /PROC_BGRT * INTERNAL_WRITE * PCI_C_BE2
* /MEMCLK * /ADD_STOP
CAS3 =
REF_ACCESS
+ MUX * MEM_ACCESS * ST1 * /INTERNAL_WRITE * MEMCLK * DELAY_IN
+ MUX * MEM_ACCESS * ST1 * /INTERNAL_WRITE * CAS3 * DELAY_IN
+ MUX * MEM_ACCESS * ST1 * /INTERNAL_WRITE * CAS3 * /MEMCLK
+ MUX * MEM_ACCESS * ST1 * PROC_BGRT * INTERNAL_WRITE * WE3 * /MEMCLK
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