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參數(shù)資料
| 型號(hào)： | 030_PCI |
| 英文描述： | Using a PCI Bus as the I/O Bus on an Am29030 Microprocessor Design |
| 中文描述： | 用的I / O上Am29030微處理器設(shè)計(jì)的PCI總線總線 |
| 文件頁數(shù)： | 20/25頁 |
| 文件大?。?/td> | 352K |
| 代理商： | 030_PCI |
AMD
4
Title
The Am29030 processor address is enabled onto the
PCI bus with the term ADD_EN during the time that
PCI_FRAME is True while PCI_FRAME_D (delayed by
one clock PCI_FRAME) is False. This represents the
first cycle on the PCI bus. During this cycle, the
PCI_C_BEx lines output the appropriately decoded
control information. The only cycles this design supports
in master mode are:
Memory reads and writes
(A31=1, A30=0, PROC_IO_MEM=0)
Configuration reads and writes
(A31=1, A30=1, PROC_IO_MEM=0)
I/O reads and writes
(A31=1, A30=X, PROC_IO_MEM=1)
Configuration reads and writes also assert PCI_IDSELx
with the decode performed on the A29 and A28 address
bits. When PCI_FRAME_D becomes True, control goes
to the data portion of the cycle (PCI_DATA_CYCLE is
True) and the data bus is enabled with DATA_EN.
PCI_FRAME_D stays True until the last PCI_TRDY is
generated.
The data direction is handled by DATA_DIR. All
PCI_C_BEx signals are driven True during the data
cycle if the cycle is a read, or they are driven with the BEx
off the Am29030 processor during a write to the PCI bus.
On the PCI bus, a device indicates that it has been se-
lected by asserting a signal PCI_DEVSEL. However, if
no device responds, the Am29030 processor does not
terminate the transaction because no PROC_RDY is
asserted and there is a bus lock. To break this lock, a de-
fault timer is put into this design in the form of a 3-bit
counter (CT0, CT1, CT2) that gives the peripherals
8 clock cycles to respond. If no PCI_DEVSEL is re-
turned, then an Am29030 processor PROC_ERR is
generated. Additionally, PROC_ERR is generated in
normal cycles if the responding peripheral also asserts
PCI_STOP. During the data cycle, PCI_IRDY is driven
True at all times and PCI_TRDY is passed to the proces-
sor on PROC_RDY to signal the end of any given cycle
on the PCI bus.
For a PCI master access, a similar transaction takes
place in reverse if the incoming PCI address bus bit
A31=1 and A30=0. Every address issued on the PCI bus
is captured in the address register by the ADD_CLK line
being active with PCI_FRAME set to True and
PCI_FRAME_D set to False. The address register
(ADD_REG_EN) is always enabled onto the Am29030
processor address bus if any of the PCI_BGRTx signals
are True, which means the Am29030 processor does
not control its address bus.
If the PCI cycle is for the local memory system, then the
internal node DEV_SEL_NODE goes active, thereby
deactivating
the
three-state
of
the
control
for
PCI_STOP, PCI_DEVSEL, and PCI_TRDY, and enab-
ling the data bus drivers through the DATA_EN term.
Since the PCI bus gives the condition for read and write
under the control portion of the PCI bus, and does not
keep a write line active through the whole cycle, this fact
is captured on an internal node INTERNAL_WRITE.
This then controls the direction of the data buffers during
a PCI master cycle. INTERNAL_WRITE also drives the
WRITE line of the processor for the memory subsystem
during this time. PCI_TRDY then becomes MEM_RDY
as the state machine for the local memory goes through
its paces. If bursting is being done, the ADD_INC signal
tells the 22V10 the A9–A2 captured address to incre-
ment to the next address. If roll over is detected in the
22V10 by the ADD_STOP signal, then a PCI_STOP is
asserted, which says a new bus address is needed.
Memory Control
Memory control becomes almost a direct graft of that de-
scribed in the
EZ-030 Demonstration Board Theory of
Operation application note. The same state machines
are implemented with the exception that accommoda-
tion is now made for more than one master to access
memory. REF_ACCESS still has top priority to do its job
to refresh the memory array. IDLE has more terms add-
ed to it to support the processor doing a local memory
cycle and the PCI bus doing its master cycle. PCI bus is
indicated by the PROC_BGRT set to False and the
PCI_DATA_CYCLE set to True. MEM_ACCESS is
started in the same manner as before and held as long
as burst is True for the Am29030 processor.
PCI, though, indicates that it is on its last cycle by deas-
serting PCI_FRAME, which has a similar control to the
Am29030 processor BURST signal. However, for a
complete cycle to take place, both TRDY and IRDY on
the PCI bus must be True so this is taken into account in
the equations for MEM_ACCESS, MEM_RDY, and
ADD_INC. If at any time, the PCI bus suspends the
memory access, then reads and writes occur to the
same address and are simply repeated because this is a
single-cycle memory unit.
RAS and CAS Decode
The RAS and CAS decode portion of the equations are
essentially the same as in the EZ-030 board application
note, with the exception that a new equation was added
to account for the source of the byte enable control.
When a local cycle is performed from the Am29030 pro-
cessor, the byte enables come from the processor on
the BEx pins. During a PCI cycle, they are issued on the
PCI_C_BEx pins on the PCI bus interface. Internal write
is used as the read/write indication (as was mentioned
before) because the PCI bus transfers the state of the
transfer on the first cycle and then does not retain a write
line for the remainder of the transaction.
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