參數(shù)資料
型號(hào)： 0W633-001-XTP
廠商： ON Semiconductor
文件頁數(shù)： 15/30頁
文件大?。?/td> 0K
描述： IC AUDIO PROCESSOR AD/DA 57CABGA
標(biāo)準(zhǔn)包裝： 5,000
系列： BelaSigna® 250
類型： 音頻處理器
應(yīng)用： 便攜式設(shè)備
安裝類型： 表面貼裝
封裝/外殼： 57-VFBGA
供應(yīng)商設(shè)備封裝： 57-CABGA（5x5）
包裝： 帶卷 (TR)
BELASIGNA 250
http://onsemi.com
22
ClockGeneration Circuitry
The chip operates with five clock domains to provide
flexibility in the control of peripherals, the selection of
sampling frequencies and the configuration of interface
communication speeds. The five clock domains are as
follows in Table 10. The base clock for all operations on the
BELASIGNA 250 chip is the system clock (SYS_CLK).
This clock may be acquired from one of three sources: the
main onchip oscillator, the system standby clock or an
external clock signal.
Table 10. CLOCK DOMAINS
Clock Name
Description
Used For
SYS_CLK
System clock
All onchip processors such as RCore, WOLA, IOP
MCLK
Main clock
All A/D and D/A converters
PCLK
Peripheral clock
Debug port, remote control, watchdog timer
WOLACLK
WOLA clock
WOLA module computations
UCLK
User clock
Can be programmed to provide a dedicated clock for an external device
The internal RC oscillator is characterized to operate up
to a frequency of 5.12 MHz. To operate properly using this
internal clock, BELASIGNA 250 has to be calibrated, and
the calibration values are to be stored within a nonvolatile
memory (usually an SPI EEPROM). When calibration isn’t
possible, BELASIGNA 250 can operate with an externally
supplied SYS_CLK, in this case, it is qualified for operation
up to 50 MHz.
The sampling frequency for all A/D and D/A converters
depends on MCLK. When MCLK is 1.28 MHz, sampling
frequencies up to 20 kHz can be selected. When MCLK is
1.92 MHz sampling frequencies up to 30 kHz can be
selected. For MCLK equal to 2.56 MHz sampling
frequencies up to 40 kHz can be selected. For MCLK equal
to 3.84 MHz, sampling frequencies up to 60 kHz can be
selected.
The WOLA clock (WCLK) feature allows WOLA
operations to be performed at a frequency slower than
SYS_CLK. This feature allows the dynamic current
consumption related to the digital blocks to be “spread” over
a longer period of time, smoothing the system’s dynamic
current draw, which can affect the audio signal.
The user clock (UCLK) can be used to provide a clock
signal to an external component, independently from the
EXT_CLK pin functionality. It can be derived from
SYS_CLK with a variety of derivation factors, or can be
connected to MCLK or even PCLK. One instance in which
it is beneficial to use this feature is when a continuous
external clock output is required but when EXT_CLK is
already being used to provide SYS_CLK to BELASIGNA
250.
Power Supply Unit
Voltage Modes
BELASIGNA 250 can operate in three different power
supply modes: high, low and double voltage. These modes
allow BELASIGNA 250 to integrate into a wider variety of
devices with a range of voltage supplies and
communications levels. The power supply modes are
described below:
High voltage (HV) power supply mode:
BELASIGNA 250 operates from a nominal supply of
1.8 V on VBAT, but this can scale depending on
available supply. All digital sections of the system,
including digital I/O pads, run from the same voltage as
supplied on VBAT. This mode is preferable in designs
where a very stable supply is available and
BELASIGNA 250 will be interfacing to other digital
systems at the same voltage. This mode is also
necessary for higher than 5.12 MHz system clocks.
Low voltage (LV) power supply mode:
BELASIGNA 250 operates from a nominal supply of
1.25 V. The WOLA, the RCore and all digital I/O pads
run from a 1 V regulated supply. The low voltage
operation of the processing cores is very
powerefficient, but the system clock should be kept
under 5.12 MHz to ensure proper operation.
Double voltage (DV) power supply mode:
BELASIGNA 250 operates from a nominal supply of
1.25 V. The WOLA, the RCore and all digital I/O pads
run from the onchip charge pump which regulates
internal voltage up to 2 V. This allows
BELASIGNA 250 to communicate with higher voltage
systems like a 1.8 V EEPROM when running on a
lower supply voltage. However, a specific level
translation mechanism has been designed to allow
BELASIGNA 250 to communicate with an SPI
EEPROM in low voltage mode as well. This voltage
mode is not suitable for normal operation, processing in
this mode may result in audible audio artifacts. Most
BELASIGNA 250 applications run in high voltage
mode.
PoweronReset (POR) and Booting Sequence
At POR, all control registers and RCore registers are put
into known default states. During the poweron procedure,
all audio outputs are muted; all RCore registers and all
control registers (analog and digital) are set to default
values. (Please contact ON Semiconductor for more
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