參數(shù)資料
型號(hào)： 0W633-001-XTP
廠商： ON Semiconductor
文件頁(yè)數(shù)： 9/30頁(yè)
文件大?。?/td> 0K
描述： IC AUDIO PROCESSOR AD/DA 57CABGA
標(biāo)準(zhǔn)包裝： 5,000
系列： BelaSigna® 250
類型： 音頻處理器
應(yīng)用： 便攜式設(shè)備
安裝類型： 表面貼裝
封裝/外殼： 57-VFBGA
供應(yīng)商設(shè)備封裝： 57-CABGA（5x5）
包裝： 帶卷 (TR)
BELASIGNA 250
http://onsemi.com
17
Weighted OverlapAdd (WOLA) Filterbank Coprocessor
Figure 4. WOLA Filterbank Coprocessor Architecture
Timedomain
output
3. Filterbank
Synthesis
(Length: Ls = La/DF)
2. Gain
Application
(Real or Complex)
1. Filterbank
Analysis
(Length: La)
Timedomain
input
R
N/2 bands
(0 to Nyquist)
R
Band
Processing
Band
Processing
Band
Processing
Down
Sampling
Up
Sampling
The
WOLA
coprocessor
performs
lowdelay,
highfidelity filterbank processing to provide efficient
timefrequency processing and aliasfree gain adjustments.
The WOLA coprocessor stores intermediate data values as
well as program code and window coefficients in its own
memory space. Audio data are accessed directly from the
input and output FIFOs where they are automatically
managed by the IOP.
The WOLA coprocessor can be configured to provide
different sizes and types of transforms, such as mono, simple
stereo or full stereo configurations. The number of bands,
the stacking mode (even or odd), the oversampling factor
and the shape of the analysis and synthesis windows used are
all configurable. The selected set of parameters affects both
the frequency resolution, the group delay through the
WOLA coprocessor and the number of cycles needed for
complete execution.
The WOLA coprocessor can generate both real and
complex data or energy values that represent the energy in
each band. Either real or complex gains can be applied to the
data. Complex gains provide means for phase adjustments,
which is useful in subband directional hearing aid
applications. The RCore always has access to these values
through shared memories. All parameters are configurable
with microcode, which is used to control the WOLA
coprocessor during execution.
The RCore initiates all WOLA functions (analysis, gain
application, synthesis) through dedicated control registers.
A dedicated interrupt is used to signal completion of a
WOLA function.
A large number of standard WOLA microcode
configurations are delivered with the BELASIGNA 250
Evaluation and Development Kit (EDK). These
configurations have been specially designed for low group
delay and high fidelity.
Input/Output Processor (IOP)
The IOP is an audiooptimized configurable DMA unit
for audio data samples. It manages the collection of data
from the A/D converters to the input FIFO and feeds digital
data to the audio output stage from the output FIFO.
The IOP places and retrieves FIFO data in memories
shared with the RCore. Each FIFO (input and output) has
two memory interfaces. The first corresponds with the
normal FIFO. Here the address of the most recent input
block changes as new blocks of samples arrive. The second
corresponds with the Smart FIFO. In this scheme the address
of the most recent input block is fixed. The Smart FIFO
interface is especially useful for timedomain filters.
In the case where the WOLA coprocessor and the IOP no
longer work together as a result of a low battery condition,
an IOP endofbatterylife automute feature is available.
The IOP can be configured to access data in the FIFOs in
four different audio modes that are shown in Figure 8.
Mono mode: Input samples are stored sequentially in
the input FIFO. Output samples are stored sequentially
in the output FIFO.
Simple stereo mode: Input samples from the two
channels are interleaved in the input FIFO. Output
samples for the single output channel are stored in the
lower part of the output FIFO.
Digital mixed mode: Input samples from the two
channels are stored in each half of the input FIFO.
Output samples for the single output channel are stored
in the lower half of the output FIFO.
Full stereo mode: Input samples from the two channels
are interleaved in the input FIFO. Output samples for
the two output channels are also interleaved in the
output FIFO.
相關(guān)PDF資料
PDF描述
AD7492ARU IC ADC 12BIT W/REF W/CLK 24TSSOP
VI-B3V-MW-F1 CONVERTER MOD DC/DC 5.8V 100W
VI-2NP-CU-F1 CONVERTER MOD DC/DC 13.8V 200W
VI-B3T-MW-F4 CONVERTER MOD DC/DC 6.5V 100W
AD7851KRZ-REEL IC ADC 14BIT SRL 333KSPS 24-SOIC
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
0W633-002-XTP 功能描述:音頻模/數(shù)轉(zhuǎn)換器 IC AUDIO AD/DA RoHS:否 制造商:Wolfson Microelectronics 轉(zhuǎn)換速率: 分辨率: ADC 輸入端數(shù)量: 工作電源電壓: 最大工作溫度: 最小工作溫度: 安裝風(fēng)格: 封裝 / 箱體: 封裝:
0W633-004-XTP 功能描述:音頻模/數(shù)轉(zhuǎn)換器 IC AUDIO AD/DA RoHS:否 制造商:Wolfson Microelectronics 轉(zhuǎn)換速率: 分辨率: ADC 輸入端數(shù)量: 工作電源電壓: 最大工作溫度: 最小工作溫度: 安裝風(fēng)格: 封裝 / 箱體: 封裝:
0W635-004-XTP 功能描述:IC DSP EZAIRO 5920 SMD 制造商:on semiconductor 系列:* 零件狀態(tài):有效 標(biāo)準(zhǔn)包裝:250
0W651002EVK 制造商:ON Semiconductor 功能描述:0W651002EVK - Boxed Product (Development Kits)
0W653-003-XDS 功能描述:音頻模/數(shù)轉(zhuǎn)換器 IC AUDIO AD/DA RoHS:否 制造商:Wolfson Microelectronics 轉(zhuǎn)換速率: 分辨率: ADC 輸入端數(shù)量: 工作電源電壓: 最大工作溫度: 最小工作溫度: 安裝風(fēng)格: 封裝 / 箱體: 封裝:
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*