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參數(shù)資料
| 型號： | 100201200 |
| 英文描述： | DURCHGANGSVERBINDUNG GERADE 12MM |
| 中文描述： | DURCHGANGSVERBINDUNG收聽12毫米 |
| 文件頁數(shù)： | 1/17頁 |
| 文件大?。?/td> | 269K |
| 代理商： | 100201200 |
Philips Semiconductors Programmable Logic Devices
Product specification
10H20EV8/10020EV8
ECL programmable array logic
113
October 22, 1993
853–1423 11164
DESCRIPTION
The 10H20EV8/10020EV8 is an ultra
high-speed universal ECL PAL device.
Combining versatile output macrocells with a
standard AND/OR single programmable
array, this device is ideal in implementing a
user’s custom logic. The use of Philips
Semiconductors state-of-the-art bipolar oxide
isolation process enables the
10H20EV8/10020EV8 to achieve optimum
speed in any design. The SNAP design
software package from Philips
Semiconductors simplifies design entry
based upon Boolean or state equations.
The 10H20EV8/10020EV8 is a two-level logic
element comprised of 11 fixed inputs, an
input pin that can either be used as a clock or
12th input, 90 AND gates, and 8 Output Logic
Macrocells. Each Output Macrocell can be
individually configured as a dedicated input,
dedicated output with polarity control, a
bidirectional I/O, or as a registered output
that has both output polarity control and
feedback to the AND array. This gives the
part the capability of having up to 20 inputs
and eight outputs.
The 10H20EV8/10020EV8 has a variable
number of product terms that can be OR’d
per output. Four of the outputs have 12 AND
terms available and the other four have 8
terms per output. This allows the designer the
extra flexibility to implement those functions
that he couldn’t in a standard PAL device.
Asynchronous Preset and Reset product
terms are also included for system design
ease. Each output has a separate output
enable product term. Another feature added
for the system designer is a power-up Reset
on all registered outputs.
The 10H20EV8/10020EV8 also features the
ability to Preload the registers to any desired
state during testing. The Preload is not
affected by the pattern within the device, so
can be performed at any step in the testing
sequence. This permits full logical verification
even after the device has been patterned.
FEATURES
Ultra high speed ECL device
– tPD = 4.5ns (max)
– tIS = 2.6ns (max)
– tCKO = 2.3ns (max)
– fMAX = 208MHz
Universal ECL Programmable Array Logic
– 8 user programmable output macrocells
– Up to 20 inputs and 8 outputs
– Individual user programmable output
polarity
Variable product term distribution allows
increased design capability
Asynchronous Preset and Reset capability
10KH and 100K options
Power-up Reset and Preload function to
enhance state machine design and testing
Design support provided via SNAP and
other CAD tools
Security fuse for preventing design
duplication
Available in 24-Pin 300mil-wide DIP and
28-Pin PLCC.
PIN CONFIGURATIONS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
F Package
I1
I2
CLK/I12
F1
F2
VCO1
F3
F4
I3
I4
I5
VCC
I11
I10
F8
F7
VCO2
F6
F5
I9
I8
I7
I6
VEE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
NC
A Package
F6
F4
I1
I2
CLK/I12
F1
F2
VCO1
NC
F3
I3
I4
I5
I6
I7
I8
I9
F5
F8
F7
VCO2
NC
I10
I11
VCC
VEE
F = Ceramic DIP (300mil-wide)
A = Plastic Leaded Chip Carrier
ORDERING INFORMATION
DESCRIPTION
ORDER CODE
DRAWING NUMBER
24-Pin Ceramic Dual In-Line (300mil-wide)
10H20EV8–4F
10020EV8–4F
0586B
28-Pin Plastic Leaded Chip Carrier
10H20EV8–4A
10020EV8–4A
0401F
PAL is a registered trademark of Monolithic Memories, Inc., a wholly owned subsidiary of Advanced Micro Devices, Inc.
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