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參數(shù)資料
| 型號： | 100201200 |
| 英文描述： | DURCHGANGSVERBINDUNG GERADE 12MM |
| 中文描述： | DURCHGANGSVERBINDUNG收聽12毫米 |
| 文件頁數(shù)： | 14/17頁 |
| 文件大?。?/td> | 269K |
| 代理商： | 100201200 |
Philips Semiconductors Programmable Logic Devices
Product specification
10H20EV8/10020EV8
ECL programmable array logic
October 22, 1993
118
DC ELECTRICAL CHARACTERISTICS 10H20EV8
0
°C ≤ Tamb ≤ +75°C, VEE = –5.2V ± 5%, VCC = VCO1 = VCO2 = GND
LIMITS4
SYMBOL
PARAMETER1
TEST CONDITIONS2
Tamb
MIN
MAX
UNITS
VOH
High level output voltage
VIN = VIH MIN or VIL MAX
0
°C
–1020
–840
+25
°C
–980
–810
mV
+75
°C
–920
–735
VOL
Low level output voltage
VIN = VIH MIN or VIL MAX
0
°C
–1950
–1630
+25
°C
–1950
–1630
mV
+75
°C
–1950
–1600
IIH
High level input current
VIN = VIH MAX
0
°C
+75
°C
220
A
IIL
Low level input current
VIN = VIL MIN
0
°C
Except I/O Pins
+75
°C
0.3
A
–IEE
Supply current
VEE = MAX
0
°C to +75°C
All inputs = VIH MAX
250
mA
DC ELECTRICAL CHARACTERISTICS 10020EV8
0
°C ≤ Tamb ≤ +85°C, –4.8V ≤ VEE ≤ –4.2V, VCC = VCO1 = VCO2 = GND
LIMITS4
SYMBOL
PARAMETER1
TEST CONDITIONS2
MIN
TYP
MAX
UNITS
VEE = –4.2V
–1020
–870
mV
VOH
High level output voltage
VIN = VIH MAX or VIL MIN
VEE = –4.5V
–1025
–955
–880
mV
VEE = –4.8V
–1035
–880
mV
Outputs
Apply VIHMIN or VILMAX to
VEE = –4.2V
–1030
mV
VOHT
High level output threshold voltage
Loaded
one input at a time, other
VEE = –4.5V
–1035
mV
with 50
inuts at VIHMAX or VILMIN.
VEE = –4.8V
–1045
mV
to –2.0V
Apply VIHMIN or VILMAX to
VEE = –4.2V
–1595
mV
VOLT
Low level output threshold voltage
± 0.010V
one input at a time, other
VEE = –4.5V
–1610
mV
inuts at VIHMAX or VILMIN.
VEE = –4.8V
–1610
mV
VEE = –4.2V
–1810
–1605
mV
VOL
Low level output voltage
Inuts at VIHMAX or VILMIN.
VEE = –4.5V
–1810
–1705
–1620
mV
VEE = –4.8V
–1830
–1620
mV
IIH
High level input current
One input under test at VIHMAX. Other inputs at
VILMIN.
220
A
IIL
Low level input current
One input under test at VILMIN. Other inputs at
VIHMAX.
0.5
A
–IEE
VEE supply current
All inputs at VIHMAX.
230
mA
NOTES:
1. All voltage measurements are referenced to the ground terminal.
2. Each ECL 10KH/100K series device has been designed to meet the DC specification after thermal equilibrium has been established.
Thermal equilibrium is established by applying power for at least 2 minutes, while maintaining transverse airflow of 2.5 meters/sec (500
linear feet/min.) over the device, mounted either in a test socket or on a printed circuit board. Test voltage values are given in the DC
operating conditions table. Conditions for testing shown in the tables are not necessarily worst case. For worst case testing guidelines, refer
to DC Testing, Chapter 1, Section 3, of the
Philips Semiconductors 10/100K ECL Data Handbook.
3. Terminals not specifically referenced can be left electrically open. Open inputs assume a logic LOW state. Any unused pins can be
terminated to –2V. If tied to VEE, it must be through a resistor > 10K. It is recommended that pins that have been programmed as RESET,
PRESET, or CLOCK inputs not be left open due to the possibility of false triggering from internally and externally generated switching
transients.
4. The specified limits represent the worst case values for the parameter. Since these worst case values normally occur at the supply voltage
and temperature extremes, additional noise immunity can be achieved by decreasing the allowable operating condition ranges.
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