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參數資料
| 型號： | 127 |
| 廠商： | Intersil Corporation |
| 英文描述： | Ultra High Frequency Transistor Arrays |
| 中文描述： | 超高頻晶體管陣列 |
| 文件頁數： | 13/13頁 |
| 文件大?。?/td> | 306K |
| 代理商： | 127 |
13
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN3076.13
December 21, 2005
HFA3046, HFA3096, HFA3127, HFA3128
Quad Flat No-Lead Plastic Package (QFN)
Micro Lead Frame Plastic Package (MLFP)
INDEX
AREA
D1/2
D1
D/2
D
E1/2
E/2
E
A
2X
0.15
B
C
0.10
B
A
M C
A
N
SEATING PLANE
N
6
3
2
2
3
e
(Nd-1)Xe
1
1
0.08
FOR ODD TERMINAL/SIDE
FOR EVEN TERMINAL/SIDE
C
C
SECTION "C-C"
NX b
A1
C
2X
C
0.15
0.15
2X
B
0
REF.
(Ne-1)Xe
REF.
5
A1
4X P
A
C
C
4X P
B
2X
A
C
0.15
A2
A3
D2
D2
2
E2
E2/2
TERMINAL TIP
SIDE VIEW
TOP VIEW
7
BOTTOM VIEW
7
5
C
C
e
e
E1
NX k
NX b
8
NX L
8
8
9
9
4X
0.10 C
/ /
9
(DATUM B)
(DATUM A)
INDEX
AREA
6
N
9
CORNER
OPTION 4X
L1
L
10
L1
L
10
L16.3x3
16 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
SYMBOL
MILLIMETERS
NOTES
MIN
NOMINAL
MAX
A
0.80
0.90
1.00
-
A1
-
-
0.05
-
A2
-
-
1.00
9
A3
0.20 REF
9
b
0.18
0.23
0.30
5, 8
D
3.00 BSC
-
D1
2.75 BSC
9
D2
1.35
1.50
1.65
7, 8, 10
E
3.00 BSC
-
E1
2.75 BSC
9
E2
1.35
1.50
1.65
7, 8, 10
e
0.50 BSC
-
k
0.20
-
-
-
L
0.30
0.40
0.50
8
N
16
2
Nd
4
3
Ne
4
3
P
-
-
0.60
9
θ
-
-
12
9
Rev. 1 6/04
NOTES:
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
3. Nd and Ne refer to the number of terminals on each D and E.
4. All dimensions are in millimeters. Angles are in degrees.
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.
8. Nominal dimensions are provided to assist with PCB Land
Pattern Design efforts, see Intersil Technical Brief TB389.
9. Features and dimensions A2, A3, D1, E1, P &
θ
are present when
Anvil singulation method is used and not present for saw
singulation.
10. Compliant to JEDEC MO-220VEED-2 Issue C, except for the E2
and D2 MAX dimension.
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