參數(shù)資料
型號(hào)： 12CE673
廠商： Microchip Technology Inc.
英文描述： HookUp/Lead Wire; Conductor Size AWG:18; No. Strands x Strand Size:65 x 36; Jacket Color:Black; Conductor Material:Copper; Jacket Material:Rubber; Leaded Process Compatible:Yes; Number of Conductors:1; Outer Diameter:0.144" RoHS Compliant: Yes
中文描述： 8引腳，8位CMOS微控制器與A / D轉(zhuǎn)換器和EEPROM數(shù)據(jù)存儲(chǔ)器
文件頁數(shù)： 14/116頁
文件大小： 671K
代理商： 12CE673
PIC12CE67X
DS40181B-page 14
Preliminary
1998 Microchip Technology Inc.
Bank 1
80h
(1)
INDF
Addressing this location uses contents of FSR to address data memory (not a physical register)
0000 0000
0000 0000
81h
OPTION
GPPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
1111 1111
1111 1111
82h
(1)
PCL
Program Counter's (PC) Least Significant Byte
0000 0000
0000 0000
83h
(1)
STATUS
IRP
(4)
RP1
(4)
RP0
TO
PD
Z
DC
C
0001 1xxx
000q quuu
84h
(1)
FSR
Indirect data memory address pointer
xxxx xxxx
uuuu uuuu
85h
TRIS
—
—
GPIO Data Direction Register
0011 1111
0011 1111
86h
—
Unimplemented
—
—
87h
—
Unimplemented
—
—
88h
—
Unimplemented
—
—
89h
—
Unimplemented
—
—
8Ah
(1,2)
PCLATH
—
—
—
Write Buffer for the upper 5 bits of the PC
---0 0000
---0 0000
8Bh
(1)
INTCON
GIE
PEIE
T0IE
INTE
GPIE
T0IF
INTF
GPIF
0000 000x
0000 000u
8Ch
PIE1
—
ADIE
—
—
—
—
—
—
-0-- ----
-0-- ----
8Dh
—
Unimplemented
—
—
8Eh
PCON
—
—
—
—
—
—
POR
—
---- --0-
---- --u-
8Fh
OSCCAL
CAL5
CAL4
CAL3
CAL2
CAL1
CAL0
—
—
1000 00--
uuuu uu--
90h
—
Unimplemented
—
—
91h
—
Unimplemented
—
—
92h
—
Unimplemented
—
—
93h
—
Unimplemented
—
—
94h
—
Unimplemented
—
—
95h
—
Unimplemented
—
—
96h
—
Unimplemented
—
—
97h
—
Unimplemented
—
—
98h
—
Unimplemented
—
—
99h
—
Unimplemented
—
—
9Ah
—
Unimplemented
—
—
9Bh
—
Unimplemented
—
—
9Ch
—
Unimplemented
—
—
9Dh
—
Unimplemented
—
—
9Eh
—
Unimplemented
—
—
9Fh
ADCON1
—
—
—
—
—
PCFG2
PCFG1
PCFG0
---- -000 ---- -000
TABLE 4-1:
PIC12CE67X SPECIAL FUNCTION REGISTER SUMMARY (CONT.)
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
Power-on
Reset
Value on
all other
Resets
(3)
Legend:
x
= unknown,
u
= unchanged,
q
= value depends on condition, - = unimplemented read as '0', r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1:
These registers can be addressed from either bank.
2:
The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose
contents are transferred to the upper byte of the program counter.
3:
Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset.
4:
The IRP and RP1 bits are reserved on the PIC12CE67X, always maintain these bits clear.
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