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參數(shù)資料
| 型號(hào)： | 141540 |
| 廠商： | Motorola, Inc. |
| 英文描述： | Monitor On-Screen Display CMOS |
| 中文描述： | 顯示器屏幕顯示的CMOS |
| 文件頁(yè)數(shù)： | 4/12頁(yè) |
| 文件大?。?/td> | 186K |
| 代理商： | 141540 |
MC141540
4
MOTOROLA
PIN DESCRIPTIONS
VSS(A) (Pin 1)
This pin provides the signal ground to the PLL circuitry.
Analog ground for PLL operation is separated from digital
ground for optimal performance.
VCO (Pin 2)
Pin 2 is a control voltage input to regulate an internal oscil-
lator frequency. See the Application Diagram for the applica-
tion values used.
RP (Pin 3)
An external RC network is used to bias an internal VCO to
resonate at the specific dot frequency. The value of the resis-
tor for this pin should be adjusted in order to set the pin volt-
age to around half VDD. See the Application Diagram for the
application values used.
VDD(A) (Pin 4)
Pin 4 is a positive 5 V supply for PLL circuitry. Analog pow-
er for PLL is separated from digital power for optimal perfor-
mance.
HFLB (Pin 5)
This pin inputs a negative polarity horizontal synchronize
signal pulse to phase lock an internal system clock gener-
ated by the on–chip VCO circuit.
SS (Pin 6)
This input pin is part of the SPI serial interface. An active
low signal generated by the master device enables this slave
device to accept data. This pin should be pulled high to termi-
nate the SPI communication.
SDA (MOSI) (Pin 7)
Data and control messages are being transmitted to this
chip from a host MCU via this wire, which is configured as a
uni–directional data line. (Detailed description of these two
protocols will be discussed in the SPI section).
SCL (SCK) (Pin 8)
A separate synchronizing clock input from the transmitter
is required for either protocol. Data is read at the rising edge
of each clock signal.
VDD (Pin 9)
This is the power pin for the digital logic of the chip.
VFLB (Pin 10)
Similar to Pin 5, this pin inputs a negative polarity vertical
synchronize signal pulse.
HTONE (Pin 11)
This pin outputs a logic high during windowing except
when graphics or characters are being displayed. It is used
to lower the external R, G, and B amplifiers’ gain to achieve a
transparent windowing effect.
FBKG (Pin 12)
This pin outputs a logic high while displaying characters or
windows when the FBKGC bit in the frame control register is
0, and output a logic high only while displaying characters
when the FBKGC bit is 1. It is defaulted to high–impedance
state after power–on, or when there is no output. An external
10 k
resistor pulled low is recommended to avoid level tog-
gling caused by hand effect when there is no output.
B,G,R (Pins 13,14,15)
MOSD color output is TTL level RGB to the host monitor.
These three signals are active high output pins that are in a
high–impedance state when MOSD is disabled.
VSS (Pin 16)
This is the ground pin for the digital logic of the chip.
SYSTEM DESCRIPTION
MC141540 is a full–screen memory architecture. Refresh
is performed by the built–in circuitry after a screenful of dis-
play data has been loaded through the serial bus. Only
changes to the display data need to be input afterward.
Serial data, which includes screen mapping address, dis-
play information, and control messages, are transmitted via
the SPI bus. Figure 2 contains the SPI protocol operating
procedure.
Data is received from the serial port and stored by the
memory management circuit. Line data is stored in a row
buffer for display and refreshing. During this storing and re-
trieving cycle, bus arbitration logic patrols the internal traffic
to make sure that no crashes occur between the slower seri-
al bus receiver and the fast ‘screen–refresh’ circuitry. After
the full–screen display data is received through one of the
serial communication interfaces, the link can be terminated if
a change of the display is not required.
The bottom half of the block diagram contains the hard-
ware functions for the entire system. It performs all the
MOSD functions such as programmable vertical length (from
16 lines to 63 lines), display clock generation (which is phase
locked to the incoming horizontal sync signal at Pin 5 HFLB),
bordering or shadowing, and multiple windowing.
COMMUNICATION PROTOCOLS
Serial Peripheral Interface (SPI)
SPI is a three–wire serial communication link that requires
separate clock (SCK) and data (MOSI) lines. In addition, an
SS slave select pin is controlled by the master transmitter to
initiate the receiver.
Operating Procedure
To initiate SPI transmission, the SS pin is pulled low by the
master device to enable MC141540 to accept data. The SS
input line must be a logic low prior to the occurrence of SCK,
and remain low until and after the last (eighth) SCK cycle. Af-
ter all data has been sent, the SS pin is then pulled high by
the master to terminate the transmission. No slave address
is needed for SPI. Hence, row and column address informa-
tion and display data can be sent immediately after the SPI is
initiated.
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