參數(shù)資料
型號(hào)： 1894-40KLFT
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 網(wǎng)絡(luò)接口
英文描述： DATACOM, INTERFACE CIRCUIT, QCC40
封裝： 6 X 6 MM, ROHS COMPLIANT, QFN-40
文件頁(yè)數(shù)： 30/52頁(yè)
文件大?。?/td> 459K
代理商： 1894-40KLFT
ICS1894-40
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE
PHYCEIVER
IDT / ICS 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 36
ICS1894-40
REV C 092909
MII Management Interface Timing
The table below lists the significant time periods for the MII Management Interface timing (which consists of timings
of signals on the MDC and MDIO pins). The MII Management Interface Timing Diagram figure shows the timing
diagram for the time periods.
The ICS1894-40 is tested at 25 MHz (a 40ns period) with a 50pF load. Designs must account for all board loading
of MDC.
MII Management Interface Timing Diagram
Time
Period
Parameter
Conditions
Min.
Typ.
Max. Units
t1
MDC Minimum High Time
–
160
–
ns
t2
MDC Minimum Low Time
–
160
–
ns
t3
MDC Period
–
400
–
ns
t4
MDC Rise Time to MDIO Valid
–
0
–
300
ns
t5
MDIO Setup Time to MDC
–
10
–
ns
t6
MDIO Hold Time after MDC
–
10
–
ns
MDC
MDIO
(Output)
MDC
MDIO
(Input)
t1
t2
t3
t4
t5
t6
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