參數(shù)資料
型號： 1894-40KLFT
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 網(wǎng)絡(luò)接口
英文描述： DATACOM, INTERFACE CIRCUIT, QCC40
封裝： 6 X 6 MM, ROHS COMPLIANT, QFN-40
文件頁數(shù)： 38/52頁
文件大?。?/td> 459K
代理商： 1894-40KLFT
ICS1894-40
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE
PHYCEIVER
IDT / ICS 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 43
ICS1894-40
REV C 092909
100M Media Independent Interface: Input-to-Carrier Assertion/De-Assertion
The table below lists the significant time periods for the 100M MDI input-to-carrier assertion/de-assertion. The time
periods consist of timings of signals on the following pins:
TP_RX (that is, TP_RXP and TP_RXN)
CRS
COL
The 100M MDI Input to Carrier Assertion/De-Assertion Timing Diagram shows the timing diagram for the time
periods.
The IEEE maximum is 20 bit times.
The IEEE minimum is 13 bit times, and the maximum is 24 bit times.
100M MDI Input to Carrier Assertion/De-Assertion Timing Diagram
Time
Period
Parameter
Conditions
Min.
Typ. Max.
Units
t1
First Bit of /J/ into TP_RX to CRS Assert
–
10
–
14
Bit times
t2
First Bit of /J/ into TP_RX while
Transmitting Data to COL Assert
Half-Duplex Mode
9
–
13
Bit times
t3
First Bit of /T/ into TP_RX to CRS
De-Assert
–13
–
18
Bit times
t4
First Bit of /T/ Received into TP_RX to
COL De-Assert
Half-Duplex Mode
13
–
18
Bit times
t1
t2
t3
t4
First bit
First bit of /T/
Shown
unscrambled.
TP_RX
CRS
COL
相關(guān)PDF資料
PDF描述
1895230000 15 A, STRIP TERMINAL BLOCK, 2 ROWS, 2 DECKS
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參數(shù)描述
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