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參數(shù)資料
| 型號： | 20068 |
| 英文描述： | and Am29243? EH Controller Data Sheet |
| 中文描述： | 和Am29243？高血壓控制器數(shù)據(jù)表 |
| 文件頁數(shù)： | 12/36頁 |
| 文件大小： | 428K |
| 代理商： | 20068 |
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P R E L I M I N A R Y
12
Am29240 EH Microcontroller Series
MEMCLK
Memory Clock (output)
MEMCLK is an output clock only. It operates at the sys-
tem operating frequency, which is half of the INCLK fre-
quency. Most processor inputs and outputs are
synchronous to MEMCLK. Note that MEMCLK as an in-
put is not supported on the Am29240EH microcontroller
series.
MEMDRV
MEMCLK Drive Enable
(input, internal pull-up resistor)
The MEMDRV signal is reserved on the Am29240EH
microcontroller series. This pin should be either tied
High or left unconnected.
PACK
Parallel Port Acknowledge (output, synchronous)
This signal is used by the processor to acknowledge a
transfer from the host or to indicate to the host that data
has been placed on the port.
PAUTOFD
Parallel Port Autofeed (input, asynchronous)
This signal is used by the host to indicate how line feeds
should be performed or is used to indicate that the host
is busy and cannot accept a data transfer.
PBUSY
Parallel Port Busy (output, synchronous)
This indicates to the host that the Parallel Port is busy
and cannot accept a data transfer.
PIACS5–PIACS0
Peripheral Chip Selects, Regions 5–0
(output, synchronous)
These signals are used to select individual peripheral
devices. DMA channels may be programmed to use
dedicated chip selects during an external peripheral
access.
PIAOE
Peripheral Output Enable (output, synchronous)
This signal enables the selected peripheral device to
drive the ID bus.
PIAWE
Peripheral Write Enable (output, synchronous)
This signal causes data on the ID bus to be written into
the selected peripheral.
PIO15–PIO0
Programmable Input/Output
(input/output, asynchronous)
These signals are available for direct software control
and inspection. PIO15–PIO8 may be individually pro-
grammed to cause processor interrupts. These signals
have special hardening against metastable states, al-
lowing them to be driven with slow-transition-time
signals.
The PIO signals are sampled during a processor reset.
After reset, the sampled value is held in the PIO Input
Register. This sampled value is supplied the first time
this register is read, unless the read is preceded by write
to the PIO Input Register or by a read or write of any oth-
er PIO register. This may be used to indicate system
configuration information to the processor during a
reset.
POE
Parallel Port Output Enable (output, synchronous)
This signal enables an external data buffer containing
data from the host to drive the ID Bus.
PSTROBE
Parallel Port Strobe (input, asynchronous)
This signal is used by the host to indicate that data is on
the Parallel Port or to acknowledge a transfer from the
processor.
PSYNC
Page Synchronization (input/output, asynchronous)
This signal indicates the beginning of a raster page. This
signal is supported on the Am29240EH and
Am29245EH microcontrollers only.
PWE
Parallel Port Write Enable (output, synchronous)
This signal writes a buffer with data on the ID Bus. Then,
the buffer drives data to the host.
R/W
Read/Write (output, synchronous)
During an external ROM, DRAM, DMA, or PIA access,
this signal indicates the direction of transfer: High for a
read and Low for a write.
RAS3–RAS0
Row Address Strobe, Banks 3–0
(output, synchronous)
A High-to-Low transition on one of these signals causes
a DRAM in the corresponding bank to latch the row ad-
dress and begin an access. RAS3 starts an access in
DRAM Bank 3, and so on. These signals also are used in
other special DRAM cycles.
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