參數(shù)資料
型號: 2032E
廠商: Lattice Semiconductor Corporation
英文描述: In-System Programmable SuperFAST⑩ High Density PLD
中文描述: 在系統(tǒng)可編程超快⑩高密度可編程邏輯器件
文件頁數(shù): 6/14頁
文件大?。?/td> 173K
代理商: 2032E
Specifications
ispLSI 2032E
6
External Timing Parameters
Over Recommended Operating Conditions
t
pd1
t
pd2
f
max
f
max (Ext.)
f
max (Tog.)
t
su1
t
co1
t
h1
t
su2
t
co2
t
h2
t
r1
t
rw1
t
ptoeen
t
ptoedis
t
goeen
t
goedis
t
wh
t
wl
UNITS
-135
MIN.
137
TEST
COND.
1. Unless noted otherwise, all parameters use a GRP load of four GLBs, 20 PTXOR path, ORP and Y0 clock.
2. Refer to Timing Model in this data sheet for further details.
3. Standard 16-bit counter using GRP feedback.
4. Reference Switching Test Conditions section.
Table 2-0030B/2032E
1
1
( )
-110
MIN.
111
MAX.
7.5
10.0
MAX.
10.0
13.0
DESCRIPTION
#
2
4
PARAMETER
A
A
A
1
2
3
Data Propagation Delay, 4PT Bypass, ORP Bypass
Data Propagation Delay
Clock Frequency with Internal Feedback
3
ns
ns
MHz
A
4
5
6
7
8
Clock Frequency with External Feedback
Clock Frequency, Max. Toggle
GLB Register Setup Time before Clock, 4 PT Bypass
GLB Register Clock to Output Delay, ORP Bypass
GLB Register Hold Time after Clock, 4 PT Bypass
MHz
MHz
ns
ns
ns
0.0
A
B
C
B
C
9
GLB Register Setup Time before Clock
10 GLB Register Clock to Output Delay
11 GLB Register Hold Time after Clock
12 External Reset Pin to Output Delay, ORP Bypass
13 External Reset Pulse Duration
14 Input to Output Enable
15 Input to Output Disable
16 Global OE Output Enable
17 Global OE Output Disable
5.5
0.0
5.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
18 External Synchronous Clock Pulse Duration, High
19 External Synchronous Clock Pulse Duration, Low
3.0
3.0
ns
ns
100
167
4.0
4.5
5.5
9.0
12.0
12.0
6.0
6.0
77.0
125
5.5
0.0
7.5
0.0
6.5
4.0
4.0
5.5
6.5
12.5
14.5
14.5
7.0
7.0
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