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參數(shù)資料
| 型號(hào)： | 2096E |
| 廠商： | Lattice Semiconductor Corporation |
| 英文描述： | In-System Programmable SuperFAST⑩ High Density PLD |
| 中文描述： | 在系統(tǒng)可編程超快⑩高密度可編程邏輯器件 |
| 文件頁(yè)數(shù)： | 2/11頁(yè) |
| 文件大?。?/td> | 142K |
| 代理商： | 2096E |
Specifications
ispLSI 2096E
2
Functional Block Diagram
Figure 1. ispLSI 2096E Functional Block Diagram
the VCCIO pins to a common 5V or 3.3V power supply,
I/O output levels can be matched to 5V or 3.3V compat-
ible voltages. When connected to a 5V supply, the I/O
pins provide PCI-compatible output drive.
Eight GLBs, 32 I/O cells, two dedicated inputs and two
ORPs are connected together to make a Megablock (see
Figure 1). The outputs of the eight GLBs are connected
to a set of 32 universal I/O cells by the two ORPs. Each
ispLSI 2096E device contains three Megablocks.
The GRP has as its inputs, the outputs from all of the
GLBs and all of the inputs from the bi-directional I/O cells.
All of these signals are made available to the inputs of the
GLBs. Delays through the GRP have been equalized to
minimize timing skew.
Clocks in the ispLSI 2096E device are selected using the
dedicated clock pins. Three dedicated clock pins (Y0, Y1,
Y2) or an asynchronous clock can be selected on a GLB
basis. The asynchronous or Product Term clock can be
generated in any GLB for its own clock.
Programmable Open-Drain Outputs
In addition to the standard output configuration, the
outputs of the ispLSI 2096E are individually program-
mable, either as a standard totem-pole output or an
open-drain output. The totem-pole output drives the
specified Voh and Vol levels, whereas the open-drain
output drives only the specified Vol. The Voh level on the
open-drain output depends on the external loading and
pull-up. This output configuration is controlled by a pro-
grammable fuse. The default configuration when the
device is in bulk erased state is totem-pole configuration.
The open-drain/totem-pole option is selectable through
the ispDesignEXPERT software tools.
A0
A3
A1
A2
B7
B4
B6
B5
O
O
I
I
Global
Routing
Pool
(GRP)
C
C
C
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
T
I
I
I
I
I
I
I
I
I
I
I
I
Y
Y
Y
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
I/O 63
I/O 62
I/O 61
I/O 60
I/O 59
I/O 58
I/O 57
I/O 56
I/O 55
I/O 54
I/O 53
I/O 52
I/O 51
I/O 50
I/O 49
I/O 48
TDI/IN 0
TMS/IN 1
TDO
RESET
BSCAN
G
G
I
I
I
I
I
I
I
I
I
I
I
I
Input Bus
0917/2096E
Megablock
C7
C6
C5
C4
A4
A5
A6
A7
Output Routing Pool (ORP)
Output Routing Pool (ORP)
Input Bus
Input Bus
B0
B1
B2
B3
Output Routing Pool (ORP)
C3
C2
C1
C0
Output Routing Pool (ORP)
Input Bus
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Generic Logic
Blocks (GLBs)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 2096VE | 3.3V In-System Programmable SuperFAST⑩ High Density PLD |
| 2096VL | 2.5V In-System Programmable SuperFAST⑩ High Density PLD |
| 2097152 | 32-BIT DYNAMIC RAM MODULE |
| 209CNQ | SCHOTTKY RECTIFIER |
| 209CNQ135 | SCHOTTKY RECTIFIER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 2096E_1 | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable SuperFASTa?￠ High Density PLD |
| 209-6ES | 制造商:CTS Corporation 功能描述:THROUGH HOLE, GOLD DIP SWITCH, 6-POLE, EXTENDED ACTUATOR, BO - Rail/Tube |
| 209-6ESD | 制造商:CTS Corporation 功能描述:THROUGH HOLE, GOLD DIP SWITCH, 6-POLE, EXTENDED ACTUATOR, BO - Rail/Tube |
| 209-6ESF | 制造商:CTS Corporation 功能描述:THROUGH HOLE, GOLD DIP SWITCH, 6-POLE, EXTENDED ACTUATOR, BO - Rail/Tube |
| 209-6ESFD | 制造商:CTS Corporation 功能描述:THROUGH HOLE, GOLD DIP SWITCH, 6-POLE, EXTENDED ACTUATOR, BO - Rail/Tube |
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