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| 型號(hào)： | 21728 |
| 英文描述： | 4-Bit, Dual, Programmable Delay Line |
| 中文描述： | 接口的Am188EM的DSLAC？ / QSLAC？使用小型工業(yè)應(yīng)用筆記？ 84.0KB（PDF格式） |
| 文件頁數(shù)： | 2/11頁 |
| 文件大?。?/td> | 84K |
| 代理商： | 21728 |
2
Interfacing the Am188
TM
EM Controller to the DSLAC
TM
/QSLAC
TM
Devices Using the SSI
like the other SLAC device’s single DIO pin. The data
on this line consists of eight-bit bytes transmitted most
significant bit (MSB, D7) first, regardless of direction.
The master initiates all transfers by sending a com-
mand byte to the SLAC device. Each command has a
predetermined length (number of bytes) and direction
(read or write). For example, if the master microproces-
sor sends out command number 25 (read GX filter co-
efficients) to the DSLAC device, the DSLAC device
knows to transmit two bytes. Because the command
determines what is transmitting, master or slave; it is
important to make sure the software drivers are correct
to prevent bus contention, which could damage the de-
vices. Also, in the case of a read, the SLAC device will
not accept a new command until the old one is finished
(i.e. all of the data is clocked out). Software verification
is critical.
The clock signal (DCLK) can free run or be active only
during data transfers and is an input to the SLAC de-
vice. The DCLK maximum frequency is 4.096 MHz for
both SLAC devices. Data is clocked into the SLAC de-
vice on the rising edge of DCLK, but data is sent out on
the falling edge of DCLK. This common technique
makes it easier to satisfy setup and hold time require-
ments. DCLK can be stopped indefinitely in either the
High or Low state if the chip select input is held High.
Each of the individual SLAC devices on the MPI bus is
addressed (i.e. selected) by pulling one of the chip se-
lect inputs Low. The QSLAC device has a single chip
select for all four channels while the DSLAC device has
a separate chip select for each channel (CS1 and
CS2). The rising edge of the chip select marks or
frames the end of each byte; therefore, the chip select
line
must
go High for at least the minimum off period
before the next byte is read or written. The DSLAC de-
vice’s minimum off period is 5 μs while the QSLAC de-
vice’s minimum is 2.5 μs.
Finally, the QSLAC device does have an interrupt pin
as part of the microprocessor interface. A description of
this pin is available in the Am79Q02/03/031 QSLAC
Device Data Sheet
.
SSI HARDWARE OVERVIEW
The Synchronous Serial Interface (SSI) on the
Am188EM microcontroller was designed to provide a
low pin-count interface to application-specific inte-
grated circuits (ASICs). Fortunately, although not by
design, it is similar to the SLAC device’s MPI. Like the
MPI, the SSI is a synchronous, master/slave serial bus
protocol that allows multiple slaves on the bus. The
maximum clock rate can be as high as 20 MHz.
The SSI bus consists of four signals:
I
SCLK
I
SDATA
I
SDEN0
I
SDEN1
Each of these signals is on a separate pin. All of the
pins are shared (i.e. multiplexed) with one of the
Am188EM microcontroller’s 32 PIOs. This allows the
SSI pins to be used as PIOs if their normal SSI function
is not needed.
The SDATA pin, like DIO, is a bidirectional, three-state
serial bus. Unlike DIO, a weak pull-up or pull-down re-
sistor keeps the last value on the bus for systems that
cannot tolerate three-state inputs. The data on this pin
consists of eight-bit bytes transmitted least significant
bit (LSB, D0) first. The master/slave protocol is con-
trolled entirely with software.
The clock signal (SCLK) is only active during byte
transfers and is an output. The frequency is derived
from the processor’s internal clock by dividing it by 2, 4,
8, or 16. In the case of a 40-MHz device, this allows for
speeds up to 20 MHz as mentioned above. Like the
SLAC device, data is clocked out on the falling edge
and clocked in on the rising edge.
The two enable pins (SDEN0 and SDEN1) are outputs
and unlike the chip selects of the MPI, they are high-
level active. While the state of the SDEN pins is con-
trolled by software somewhat like a PIO, the pin must
be high for the interface to transmit or receive.
COMPARING MPI TO SSI
Table 1 summarizes the similarities and differences be-
tween the two interfaces.
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