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| 型號(hào)： | 22450C |
| 英文描述： | MicroManager Chip |
| 中文描述： | 手動(dòng)？lanSC520微控制器的客戶開(kāi)發(fā)平臺(tái)（CDP）的用戶手冊(cè) |
| 文件頁(yè)數(shù)： | 44/78頁(yè) |
| 文件大?。?/td> | 1849K |
| 代理商： | 22450C |
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élanSC520 Microcontroller Customer Development Platform User’s Manual
2-12
Memory
The memory on the élanSC520 microcontroller CDP consists of SDRAM and
Flash memory.
SDRAM
The élanSC520 microcontroller CDP can have a maximum of four rows on two
DIMMs that connect into two industry-standard, 168-pin DIMM sockets. The
DIMMs are 64-bit wide main memory, using 16/64-Mbit x 8 SDRAM chips. Note
that the SDRAM DIMMs used are 64-bits wide only because they are configured
as two rows each. Error Correction Code (ECC) is not supported on the full
SDRAM DIMMs; the ECC supports only half of the DIMM capacity. Figure 2-6
on page 2-13 shows the SDRAM configuration diagram.
The two DIMM sockets are wired to enable you to install a combination of single-
or double-sided DIMMs. This configuration yields a total of four rows of SDRAM
memory, using the two DIMM sockets. You can adjust the timing of the SDRAM
interface by using the registers in the élanSC520 microcontroller.
Table 2-2 shows the SDRAM signals and the descriptions.
Table 2-2. SDRAM Signals
SDRAM Signal
Description
CS0–CS3
Chip select signal for each row on DIMM
MA0–MA12
Memory address signals
MD0–MD31
Memory data signals
BA0–BA1
Memory bank select signal for each memory chip
DQM0–DQM3
Data byte masks
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