參數(shù)資料
型號(hào)： 22450C
英文描述： MicroManager Chip
中文描述： 手動(dòng)？lanSC520微控制器的客戶開發(fā)平臺(tái)（CDP）的用戶手冊(cè)
文件頁數(shù)： 71/78頁
文件大?。?/td> 1849K
代理商： 22450C
élanSC520 Microcontroller Customer Development Platform User’s Manual
B-5
PIO Resource Assignments
Table B-4 provides the resource assignments for the devices listed.
Table B-4. PIO Resource Assignments
PIN
CDP
PROBE
1
CDP Use
PIO
Input
PIO
Output
PIO0
GPALE
P8 D14
Drives ISA ALE via buffer U20
NA
NA
PIO1
GPBHE
P8 D12
Drives ISA BHE via buffer U20
NA
NA
PIO2
GPRDY
P8 D15
Driven by ISA IOCHRDY, IDE hard drive
IOCHRDY, Super I/O IOCHRDY, and
TIP IOCHRDY. Wired OR with 1K pullup
to 5V.
NA
NA
PIO3
GPAEN
P8 P11
Drives ISA, Super I/O, AND tip and via
buffer U20. GPAEN used by PALs U4 and
U6 for GP bus decode.
NA
NA
PIO4
GPTC
P3 D10
Drives ISA and Super I/O TC via Buffer
U20
NA
NA
PIO5
GPDRQ3
P4-16
IDE hard drive DMAREQ via R17
NA
NA
PIO6
GPDRQ2
P4-11
Super I/O DRQ0 for SIO
NA
NA
PIO7
GPDRQ1
P4-14
ISA DRQ0, 1, 2, 3, 5, 6, 7; selected by JP8
NA
NA
PIO8
GPDRQ0
P4-11
ISA DRQ0, 1, 2, 3, 5, 6, 7; selected by JP6
NA
NA
PIO9
GPDACK3
P4-20
IDE hard drive DMA_ACK via R18
NA
NA
PIO10
GPDACK2
P4-17
Super I/O DACK0 for SIO
NA
NA
PIO11
GPDACK1
P4-18
ISA DACK0, 1, 2, 3, 5, 6, 7; selected by
JP9
NA
NA
PIO12
GPDACK0
P4-15
ISA DACK0, 1, 2, 3, 5, 6, 7; selected by
JP7
NA
NA
PIO13
GPIRQ10
P4-12
Driven by ISA IRQ10, Super I/O IRQ10,
IDE hard drive IRQ, and TIP ENETIRQ
via R015; has pullup 4K7 to 5V.
NA
NA
PIO14
GPIRQ9
P4-9
Driven by ISA IRQ9, Super I/O IRQ9, and
TIP PARIRQ via R106; has pullup 4K7 to
5V.
NA
NA
PIO15
GPIRQ8
P4-10
Driven by Super I/O IRQ8 and TIP
SERIRQ1 via R107; has pullup 4K7 to
5V.
NA
NA
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