參數資料
型號: 22459
英文描述: AMD-K6 Processor Data Sheet AMD-K6E Processor Data Sheet Supplement
中文描述: 的AMD - K6處理器的數據資料的AMD - K6E處理器數據手冊補編
文件頁數: 4/10頁
文件大?。?/td> 734K
代理商: 22459
4
AMD-K6
E Embedded Processor Data Sheet Supplement
ARCHITECTURAL OVERVIEW
Figure 1 shows the block diagram for the AMD-K6E embedded processor. The sections that follow describe the fea-
tures of the part.
Figure 1.
AMD-K6E Embedded Processor Block Diagram
The AMD-K6E Processor
The AMD-K6E embedded processor is function- and
pin-compatible with the industry-leading AMD-K6
processor (Model 7). It is an excellent choice for
embedded applications that require a high-
performance x86-compatible processor such as
central office switches, network routers, point-of-sale
terminals, information appliances, and Socket 7/
Windows based single-board computers.
The AMD-K6 Processor Core
The AMD-K6E embedded processor is based on the
AMD-K6 processor (Model 7), and it maintains pin,
function, and software compatibility.
To provide industry-leading performance, the AMD-K6
processor core incorporates the innovative and
efficient RISC86 microarchitecture, a large 64-Kbyte
level-one cache (32-Kbyte dual-ported data cache,
32-Kbyte instruction cache with predecode data), a
powerful IEEE 754-compatible and 854-compatible
floating-point execution unit, and a high-performance
multimedia execution unit for executing
industry-standard MMX instructions. These features
have been combined to deliver industry leadership in
16-bit and 32-bit performance.
The AMD-K6 processor’s RISC86 microarchitecture is
a decoupled decode/execution superscalar design that
implements state-of-the-art design techniques to
achieve leading-edge performance. Advanced design
techniques implemented in the AMD-K6 include
multiple x86 instruction decode, single-clock internal
RISC operations, seven execution units that support
superscalar operation, out-of-order execution, data
forwarding, speculative execution, and register
renaming. In addition, the processor supports state-of-
the-art advanced branch prediction logic by
implementing an 8192-entry branch history table (the
industry’s only branch target cache) and a return
address stack, which combine to deliver an extremely
high prediction rate. These design techniques enable
the AMD-K6 processor to issue, execute, and retire
multiple x86 instructions per clock, resulting in
excellent scalable performance.
Designed to run both 16-bit and 32-bit software, the
AMD-K6 processor is x86 binary-code compatible.
AMD’s extensive experience through four generations
of x86 processors has been carefully integrated into
the AMD-K6 to provide complete compatibility with
Integer X
(Register) Unit
Store
Unit
Integer Y
(Register) Unit
Floating-Point
Unit
Branch
(Resolving) Unit
Store
Queue
Instruction
Control Unit
Scheduler
Buffer
(24 RISC86)
Six RISC86
Operation Issue
Out-of-Order
Execution Engine
Level-One Dual-Port Data Cache
(32 KByte)
128-Entry DTLB
Level-One Instruction Cache
(32 KByte + Predecode)
64-Entry ITLB
Dual Instruction Decoders
x86 to RISC86
Branch Logic
(8192-Entry BHT)
(16-Entry BTC)
(16-Entry RAS)
Load
Unit
Multimedia
Unit
Predecode
Logic
Level-One Cache
Controller
Socket 7
Bus
Interface
16-Byte Fetch
Four RISC86
Decode
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