參數(shù)資料
型號(hào)： 231Q1
廠商： Texas Instruments, Inc.
元件分類： CAN
英文描述： 3.3-V CAN TRANSCEIVERS
中文描述： 3.3 V的CAN收發(fā)器
文件頁數(shù)： 23/30頁
文件大?。?/td> 488K
代理商： 231Q1
SN65HVD230Q-Q1
SN65HVD231Q-Q1
SN65HVD232Q-Q1
SGLS117C
–
JUNE 2001
–
REVISED JUNE 2002
23
www.ti.com
APPLICATION INFORMATION
standby mode (listen only mode) of the SN65HVD230Q
If a logic high (> 0.75 V
CC
) is applied to R
S
(pin 8) in Figures 29 and 31, the circuit of the SN65HVD230Q enters
a low-current,
listen only
standby mode during which the driver is switched off and the receiver remains active.
In this
listen only
state, the transceiver is completely passive to the bus. It makes no difference if a slope control
resistor is in place as shown in Figure 31. The DSP can reverse this low-power standby mode when the rising
edge of a dominant state (bus differential voltage > 900 mV typical) occurs on the bus. The DSP, sensing bus
activity, reactivates the driver circuit by placing a logic low (< 1.2 V) on R
S
(pin 8).
the babbling idiot protection of the SN65HVD231Q
Occasionally, a runaway CAN controller unintentionally sends messages that completely tie up the bus (what
is referred to in CAN jargon as a babbling idiot). When this occurs, the DSP can engage the
listen-only
standby
mode to disengage the driver and release the bus, even when access to the CAN controller has been lost. When
the driver circuit is deactivated, its outputs default to a high-impedance state.
sleep mode of the SN65HVD231Q
The unique difference between the SN65HVD230Q and the SN65HVD231Q
is that both driver and receiver are
switched off in the SN65HVD231Q when a logic high is applied to R
S
(pin 8). The device remains in a very low
power-sleep mode until the circuit is reactivated with a logic low applied to R
S
(pin 8).
While in this sleep mode,
the bus pins are in a high-impedance state, while the D and R pins default to a logic high.
loop propagation delay
Transceiver loop delay is a measure of the overall device propagation delay, consisting of the delay from the
driver input to the differential outputs, plus the delay from the receiver inputs to its output.
The loop delay of the transceiver displayed in Figure 34 increases accordingly when slope control is being used.
This increased loop delay means that the total bus length must be reduced to meet the CAN bit-timing
requirements of the overall system. The loop delay becomes
≈
100 ns when employing slope control with a
10-k
resistor, and
≈
500 ns with a 100-k
resistor. Therefore, considering that the rule-of-thumb propagation
delay of typical bus cable is 5 ns/m, slope control with the 100-k
resistor decreases the allowable bus length
by the difference between the 500-ns max loop delay and the loop delay with no slope control, 70.7 ns. This
equates to (500
–
70.7 ns)/5 ns, or approximately 86 m less bus length. This slew-rate/bus length trade-off to
reduce electromagnetic interference to adjoining circuits from the bus can also be solved with a high-quality
shielded bus cable.
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