參數(shù)資料
型號(hào): 24AA32A-P
廠商: Microchip Technology Inc.
英文描述: 32K 1.8V I 2 C O Serial EEPROM
中文描述: 32K的1.8VI 2二氧化碳串行EEPROM
文件頁數(shù): 6/12頁
文件大?。?/td> 79K
代理商: 24AA32A-P
24AA32A
DS21162B-page 6
Preliminary
1996 Microchip Technology Inc.
4.0
WRITE OPERATION
4.1
Byte Write
Following the start condition from the master, the con-
trol code (four bits), the device select (three bits), and
the R/W bit which is a logic low are clocked onto the bus
by the master transmitter. This indicates to the
addressed slave receiver that a byte with a word
address will follow after it has generated an acknowl-
edge bit during the ninth clock cycle. Therefore, the next
byte transmitted by the master is the high-order byte of
the word address and will be written into the address
pointer of the 24AA32A. The next byte is the least sig-
nificant address byte. After receiving another acknowl-
edge signal from the 24AA32A the master device will
transmit the data word to be written into the addressed
memory location.
The 24AA32A acknowledges again and the master
generates a stop condition. This initiates the internal
write cycle, and during this time the 24AA32A will not
generate acknowledge signals (Figure 4-1).
4.2
Page Write
The write control byte, word address and the first data
byte are transmitted to the 24AA32A in the same way
as in a byte write. But instead of generating a stop con-
dition, the master transmits up to 32 bytes which are
temporarily stored in the on-chip page buffer and will be
written into memory after the master has transmitted a
stop condition. After receipt of each word, the five lower
address pointer bits are internally incremented by one.
If the master should transmit more than 32 bytes prior
to generating the stop condition, the address counter
will roll over and the previously received data will be
overwritten. As with the byte write operation, once the
stop condition is received, an internal write cycle will
begin. (Figure 4-2).
FIGURE 4-1:
BYTE WRITE
FIGURE 4-2:
PAGE WRITE
0 0 0 0
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
S
T
A
R
T
CONTROL
BYTE
ADDRESS
HIGH BYTE
ADDRESS
LOW BYTE
DATA
A
C
K
A
C
K
A
C
K
A
C
K
S
T
O
P
0 0 0 0
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
S
T
A
R
T
CONTROL
BYTE
ADDRESS
HIGH BYTE
ADDRESS
LOW BYTE
DATA BYTE 0
A
C
K
A
C
K
A
C
K
A
C
K
S
T
O
P
DATA BYTE 31
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