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參數(shù)資料
| 型號(hào)： | 24C01C-IST |
| 廠商： | Microchip Technology Inc. |
| 英文描述： | IC, QUAD PHY 10GX |
| 中文描述： | 一千5.0VI 2葷⑩串行EEPROM |
| 文件頁(yè)數(shù)： | 5/12頁(yè) |
| 文件大?。?/td> | 326K |
| 代理商： | 24C01C-IST |
24C01C
1997 Microchip Technology Inc.
Preliminary
DS21201A-page 5
4.0
BUS CHARACTERISTICS
The following
bus protocol
has been defined:
Data transfer may be initiated only when the bus is
not busy.
During data transfer, the data line must remain
stable whenever the clock line is HIGH. Changes
in the data line while the clock line is HIGH will be
interpreted as a START or STOP condition.
Accordingly, the following bus conditions have been
defined (Figure 4-1).
4.1
Bus not Busy (A)
Both data and clock lines remain HIGH.
4.2
Start Data Transfer (B)
A HIGH to LOW transition of the SDA line while the
clock (SCL) is HIGH determines a START condition. All
commands must be preceded by a START condition.
4.3
Stop Data Transfer (C)
A LOW to HIGH transition of the SDA line while the
clock (SCL) is HIGH determines a STOP condition. All
operations must be ended with a STOP condition.
4.4
Data Valid (D)
The state of the data line represents valid data when,
after a START condition, the data line is stable for the
duration of the HIGH period of the clock signal.
The data on the line must be changed during the LOW
period of the clock signal. There is one bit of data per
clock pulse.
Each data transfer is initiated with a START condition
and terminated with a STOP condition. The number of
the data bytes transferred between the START and
STOP conditions is determined by the master device
and is theoretically unlimited, although only the last six-
teen will be stored when doing a write operation. When
an overwrite does occur it will replace data in a first in
first out fashion.
4.5
Acknowledge
Each receiving device, when addressed, is required to
generate an acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse which is associated with this acknowledge bit.
The device that acknowledges has to pull down the
SDA line during the acknowledge clock pulse in such a
way that the SDA line is stable LOW during the HIGH
period of the acknowledge related clock pulse. Of
course, setup and hold times must be taken into
account. A master must signal an end of data to the
slave by not generating an acknowledge bit on the last
byte that has been clocked out of the slave. In this case,
the slave must leave the data line HIGH to enable the
master to generate the STOP condition (Figure 4-2).
FIGURE 4-1:
DATA TRANSFER SEQUENCE ON THE SERIAL BUS CHARACTERISTICS
FIGURE 4-2:
ACKNOWLEDGE TIMING
Note:
The 24C01C does not generate any
acknowledge bits if an internal program-
ming cycle is in progress.
(A)
(B)
(C)
(D)
(A)
(C)
SCL
SDA
START
CONDITION
ADDRESS OR
ACKNOWLEDGE
VALID
DATA
ALLOWED
TO CHANGE
STOP
CONDITION
SCL
9
8
7
6
5
4
3
2
1
1
2
3
Transmitter must release the SDA line at this point
allowing the Receiver to pull the SDA line low to
acknowledge the previous eight bits of data.
Receiver must release the SDA line at this point
so the Transmitter can continue sending data.
Data from transmitter
Data from transmitter
SDA
Acknowledge
Bit
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 24C01C-P | 1K 5.0V I 2 C ⑩ Serial EEPROM |
| 24C01C-SN | 1K 5.0V I 2 C ⑩ Serial EEPROM |
| 24C01C-ST | 1K 5.0V I 2 C ⑩ Serial EEPROM |
| 24C01C-EP | 71-255612-08P |
| 24C01C-ESN | PTSE 8C 8#20 STR PLUG |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 24C01CP | 制造商:Microchip Technology Inc 功能描述: |
| 24C01C-P | 制造商:MICROCHIP 制造商全稱:Microchip Technology 功能描述:1K 5.0V I 2 C ⑩ Serial EEPROM |
| 24C01CSN | 制造商:Microchip Technology Inc 功能描述: |
| 24C01C-SN | 制造商:MICROCHIP 制造商全稱:Microchip Technology 功能描述:1K 5.0V I 2 C ⑩ Serial EEPROM |
| 24C01C-ST | 制造商:MICROCHIP 制造商全稱:Microchip Technology 功能描述:1K 5.0V I 2 C ⑩ Serial EEPROM |
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