參數(shù)資料
型號(hào)： 24FC256
英文描述： 24AA256/LC256/FC256 Datasheet
中文描述： 24AA256/LC256/FC256數(shù)據(jù)表
文件頁數(shù)： 9/28頁
文件大?。?/td> 449K
代理商： 24FC256
2003 Microchip Technology Inc.
DS21203L-page 9
24AA256/24LC256/24FC256
6.0
WRITE OPERATIONS
6.1
Byte Write
Following the Start condition from the master, the
control code (four bits), the Chip Select (three bits) and
the R/W bit (which is a logic low) are clocked onto the
bus by the master transmitter. This indicates to the
addressed slave receiver that the address high byte will
follow after it has generated an Acknowledge bit during
the ninth clock cycle. Therefore, the next byte
transmitted by the master is the high-order byte of the
word address and will be written into the address
pointer of the 24XX256. The next byte is the Least
Significant Address Byte. After receiving another
Acknowledge signal from the 24XX256, the master
device will transmit the data word to be written into the
addressed memory location. The 24XX256 acknowl-
edges again and the master generates a Stop
condition. This initiates the internal write cycle and
during this time, the 24XX256 will not generate
Acknowledge signals (Figure 6-1). If an attempt is
made to write to the array with the WP pin held high, the
device will acknowledge the command but no write
cycle will occur, no data will be written, and the device
will immediately accept a new command. After a byte
Write command, the internal address counter will point
to the address location following the one that was just
written.
6.2
Page Write
The write control byte, word address and the first data
byte are transmitted to the 24XX256 in much the same
way as in a byte write. The exception is that instead of
generating a Stop condition, the master transmits up to
63 additional bytes, which are temporarily stored in the
on-chip page buffer and will be written into memory
once the master has transmitted a Stop condition.
Upon receipt of each word, the six lower address
pointer bits are internally incremented by one. If the
master should transmit more than 64 bytes prior to
generating the Stop condition, the address counter will
roll over and the previously received data will be over-
written. As with the byte write operation, once the Stop
condition is received, an internal write cycle will begin
(Figure 6-2). If an attempt is made to write to the array
with the WP pin held high, the device will acknowledge
the command but no write cycle will occur, no data will
be written and the device will immediately accept a new
command.
6.3
Write-Protection
The WP pin allows the user to write-protect the entire
array (0000-7FFF) when the pin is tied to V
CC
. If tied to
V
SS
or left floating, the write-protection is disabled. The
WP pin is sampled at the Stop bit for every Write
command (Figure 1-1). Toggling the WP pin after the
Stop bit will have no effect on the execution of the write
cycle.
FIGURE 6-1:
BYTE WRITE
FIGURE 6-2:
PAGE WRITE
Note:
Page write operations are limited to writing
bytes within a single physical page,
regardless
of the number of bytes actually
being written. Physical page boundaries
start at addresses that are integer
multiples of the page buffer size (or ‘page
size’) and end at addresses that are
integer multiples of [page size - 1]. If a
Page Write command attempts to write
across a physical page boundary, the
result is that the data wraps around to the
beginning of the current page (overwriting
data previously stored there), instead of
being written to the next page, as might be
expected. It is, therefore, necessary for the
application software to prevent page write
operations that would attempt to cross a
page boundary.
X
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
S
T
A
R
T
CONTROL
BYTE
ADDRESS
HIGH BYTE
ADDRESS
LOW BYTE
DATA
S
T
O
P
A
C
K
A
C
K
A
C
K
A
C
K
X = don’t care bit
S 1 0 1 0
0
A
2A
1A
0
P
X
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
S
T
A
R
T
CONTROL
BYTE
ADDRESS
HIGH BYTE
ADDRESS
LOW BYTE
DATA BYTE 0
S
T
O
P
P
A
C
K
A
C
K
A
C
K
A
C
K
DATA BYTE 63
A
C
K
X = don’t care bit
S 1 0 1 0
0
A
2A
1A
0
相關(guān)PDF資料
PDF描述
24FC32 32K 5.0V 1 MHz I 2 C Smart Serial EEPROM
24FC32-IP 32K 5.0V 1 MHz I 2 C Smart Serial EEPROM
24FC32-ISM 32K 5.0V 1 MHz I 2 C Smart Serial EEPROM
24FC32-P 32K 5.0V 1 MHz I 2 C Smart Serial EEPROM
24FC32-SM 32K 5.0V 1 MHz I 2 C Smart Serial EEPROM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
24FC256/S15K 制造商:Microchip Technology Inc 功能描述:256K, 32K X 8, 2.5V HI-SPEED S - Gel-pak, waffle pack, wafer, diced wafer on film
24FC256/W15K 制造商:Microchip Technology Inc 功能描述:256K, 32K X 8, 2.5V HI-SPEED S - Gel-pak, waffle pack, wafer, diced wafer on film
24FC256/WF15K 制造商:Microchip Technology Inc 功能描述:256K, 32K X 8, 2.5V HI-SPEED S - Gel-pak, waffle pack, wafer, diced wafer on film
24FC256E/MF 制造商:MICROCHIP 制造商全稱:Microchip Technology 功能描述:256K I2C CMOS Serial EEPROM
24FC256-E/MF 制造商:MICROCHIP 制造商全稱:Microchip Technology 功能描述:256K I2C CMOS Serial EEPROM
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購

我的聯(lián)系方式

*
*
*