參數(shù)資料
型號(hào): 24FC32-IP
廠商: Microchip Technology Inc.
英文描述: 32K 5.0V 1 MHz I 2 C Smart Serial EEPROM
中文描述: 32K的5.0V 1兆赫的I 2 C串行EEPROM智能
文件頁(yè)數(shù): 3/12頁(yè)
文件大小: 99K
代理商: 24FC32-IP
1996 Microchip Technology Inc.
DS21126B-page 3-3
24FC32
TABLE 1-3:
AC CHARACTERISTICS
FIGURE 1-2:
BUS TIMING DATA
Parameter
Symbol
1 MHz Bus
Units
Remarks
Min
Max
Clock frequency
F
CLK
0
1000
kHz
Clock high time
T
HIGH
500
ns
Clock low time
T
LOW
500
ns
SDA and SCL rise time
T
R
300
ns
(Note 1)
SDA and SCL fall time
T
F
100
ns
(Note 1)
START condition hold time
T
HD
:
STA
250
ns
After this period the first clock pulse is generated
START condition setup time
T
SU
:
STA
250
ns
Only relevant for repeated START condition
Data input hold time
T
HD
:
DAT
0
ns
Data input setup time
T
SU
:
DAT
100
ns
STOP condition setup time
T
SU
:
STO
250
ns
Output valid from clock
T
AA
350
ns
(Note 2)
Bus free time
T
BUF
500
ns
Time the bus must be free before a new trans-
mission can start
Write cycle time
T
WR
5
ms/page
Note 3
Endurance
High Endurance Block
Rest of Array
10M
1M
10M
1M
25
°
C, Vcc = 5.0V, Block Mode (Note 4)
Note 1: Not 100 percent tested.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 100 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
3: The times shown are for a single page of 8 bytes. Multiply by the number of pages loaded into the write
cache for total time.
4: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific appli-
cation, please consult the Total Endurance Model which can be obtained on our BBS or website.
SCL
SDA
IN
SDA
OUT
T
SU
:
STA
T
SP
T
AA
T
F
T
LOW
T
HIGH
T
HD
:
STA
T
HD
:
DAT
T
SU
:
DAT
T
SU
:
STO
T
BUF
T
AA
T
R
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