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參數(shù)資料
| 型號： | 24FC32-IP |
| 廠商： | Microchip Technology Inc. |
| 英文描述： | 32K 5.0V 1 MHz I 2 C Smart Serial EEPROM |
| 中文描述： | 32K的5.0V 1兆赫的I 2 C串行EEPROM智能 |
| 文件頁數(shù)： | 4/12頁 |
| 文件大?。?/td> | 99K |
| 代理商： | 24FC32-IP |
24FC32
DS21126B-page 3-4
1996 Microchip Technology Inc.
2.0
FUNCTIONAL DESCRIPTION
The 24FC32 supports a bidirectional two-wire bus and
data transmission protocol. A device that sends data
onto the bus is defined as transmitter, and a device
receiving data as receiver. The bus must be controlled
by a master device which generates the serial clock
(SCL), controls the bus access, and generates the
START and STOP conditions, while the 24FC32 works
as slave. Both master and slave can operate as
transmitter or receiver but the master device
determines which mode is activated.
3.0
BUS CHARACTERISTICS
The following
Data transfer may be initiated only when the bus is
not busy.
During data transfer, the data line must remain
stable whenever the clock line is HIGH. Changes
in the data line while the clock line is HIGH will be
interpreted as a START or STOP condition.
Accordingly, the following bus conditions have been
defined (Figure 3-1).
bus protocol
has been defined:
3.1
Bus not Busy (A)
Both data and clock lines remain HIGH.
3.2
Start Data Transfer (B)
A HIGH to LOW transition of the SDA line while the
clock (SCL) is HIGH determines a START condition. All
commands must be preceded by a START condition.
3.3
Stop Data Transfer (C)
A LOW to HIGH transition of the SDA line while the
clock (SCL) is HIGH determines a STOP condition. All
operations must be ended with a STOP condition.
3.4
Data Valid (D)
The state of the data line represents valid data when,
after a START condition, the data line is stable for the
duration of the HIGH period of the clock signal.
The data on the line must be changed during the LOW
period of the clock signal. There is one clock pulse per
bit of data.
Each data transfer is initiated with a START condition
and terminated with a STOP condition. The number of
the data bytes transferred between the START and
STOP conditions is determined by the master device.
3.5
Acknowledge
Each receiving device, when addressed, is obliged to
generate an acknowledge signal after the reception of
each byte. The master device must generate an extra
clock pulse which is associated with this acknowledge
bit.
A device that acknowledges must pull down the SDA
line during the acknowledge clock pulse in such a way
that the SDA line is stable LOW during the HIGH period
of the acknowledge related clock pulse. Of course,
setup and hold times must be taken into account.
During reads, a master must signal an end of data to
the slave by NOT generating an acknowledge bit on the
last byte that has been clocked out of the slave. In this
case, the slave (24FC32) will leave the data line HIGH
to enable the master to generate the STOP condition.
Note:
The 24FC32 does not generate any
acknowledge
bits
programming cycle is in progress.
if
an
internal
FIGURE 3-1:
DATA TRANSFER SEQUENCE ON THE SERIAL BUS
SCL
SDA
(A)
(B)
(D)
(D)
(C)
(A)
START CONDITION
ADDRESS
OR
ACKNOWLEDGE
VALID
DATA ALLOWED
TO CHANGE
STOP
CONDITION
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 24FC32-ISM | 32K 5.0V 1 MHz I 2 C Smart Serial EEPROM |
| 24FC32-P | 32K 5.0V 1 MHz I 2 C Smart Serial EEPROM |
| 24FC32-SM | 32K 5.0V 1 MHz I 2 C Smart Serial EEPROM |
| 24FC512 | 512K I2C CMOS Serial EEPROM |
| 24AA512 | 512K I2C CMOS Serial EEPROM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 24FC32-ISM | 制造商:MICROCHIP 制造商全稱:Microchip Technology 功能描述:32K 5.0V 1 MHz I 2 C Smart Serial EEPROM |
| 24FC32-P | 制造商:MICROCHIP 制造商全稱:Microchip Technology 功能描述:32K 5.0V 1 MHz I 2 C Smart Serial EEPROM |
| 24FC32-SM | 制造商:MICROCHIP 制造商全稱:Microchip Technology 功能描述:32K 5.0V 1 MHz I 2 C Smart Serial EEPROM |
| 24FC512 | 制造商:MICROCHIP 制造商全稱:Microchip Technology 功能描述:512K I2C? CMOS Serial EEPROM |
| 24FC512/S16K | 制造商:Microchip Technology Inc 功能描述:512K, 64K X 8, 2.5V HI-SPEED S - Gel-pak, waffle pack, wafer, diced wafer on film |
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