參數(shù)資料
型號: 24LC00
廠商: Microchip Technology Inc.
英文描述: 128 Bit IIC Bus Serial EEPROMs(2.5~6V,128位,IIC總線串行EEPROM)
中文描述: 128位IIC總線(2.5?6V的,128位,進(jìn)口證總線串行EEPROM的串行EEPROM)
文件頁數(shù): 6/12頁
文件大小: 182K
代理商: 24LC00
24xx00
DS21178B-page 6
1996 Microchip Technology Inc.
6.0
WRITE OPERATIONS
6.1
Byte Write
Following the start signal from the master, the device
code (4 bits), the don't care bits (3 bits), and the R/W bit
(which is a logic low) are placed onto the bus by the
master transmitter. This indicates to the addressed
slave receiver that a byte with a word address will follow
after it has generated an acknowledge bit during the
ninth clock cycle. Therefore, the next byte transmitted
by the master is the word address and will be written
into the address pointer of the 24xx00. Only the lower
four address bits are used by the device, and the upper
four bits are don’t cares. The 24xx00 will acknowledge
the address byte and the master device will then trans-
mit the data word to be written into the addressed mem-
ory location. The 24xx00 acknowledges again and the
master generates a stop condition. This initiates the
internal write cycle, and during this time the 24xx00 will
not generate acknowledge signals (Figure 7-2). After a
byte write command, the internal address counter will
not be incremented and will point to the same address
location that was just written. If a stop bit is transmitted
to the device at any point in the write command
sequence before the entire sequence is complete, then
the command will abort and no data will be written. If
more than 8 data bits are transmitted before the stop bit
is sent, then the device will clear the previously loaded
byte and begin loading the data buffer again. If more
than one data byte is transmitted to the device and a
stop bit is sent before a full eight data bits have been
transmitted, then the write command will abort and no
data will be written. The 24xx00 employs a V
CC
thresh-
old detector circuit which disables the internal erase/
write logic if the V
CC
is below 1.5V (24AA00 and
24LC00) or 3.8V (24C00) at nominal conditions.
7.0
ACKNOWLEDGE POLLING
Since the device will not acknowledge during a write
cycle, this can be used to determine when the cycle is
complete (this feature can be used to maximize bus
throughput). Once the stop condition for a write com-
mand has been issued from the master, the device ini-
tiates the internally timed write cycle. ACK polling can
be initiated immediately. This involves the master send-
ing a start condition followed by the control byte for a
write command (R/W = 0). If the device is still busy with
the write cycle, then no ACK will be returned. If no ACK
is returned, then the start bit and control byte must be
re-sent. If the cycle is complete, then the device will
return the ACK and the master can then proceed with
the next read or write command. See Figure 7-1 for flow
diagram.
FIGURE 7-1:
ACKNOWLEDGE POLLING
FLOW
FIGURE 7-2:
BYTE WRITE
Send
Write Command
Send Stop
Condition to
Initiate Write Cycle
Send Start
Send Control Byte
with R/W = 0
Did Device
Acknowledge
(ACK = 0)
Next
Operation
NO
YES
S
P
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
S
T
A
R
T
S
T
O
P
CONTROL
BYTE
WORD
ADDRESS
DATA
A
C
K
A
C
K
A
C
K
1
0
X
1
0
X
X
X
X = Don’t Care Bit
X
X
X
0
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