參數(shù)資料
型號(hào): 24LC04
廠商: Microchip Technology Inc.
英文描述: 4K/8K 2.5V I 2 C Serial EEPROMs
中文描述: 4K/8K 2.5VI 2 C串行EEPROM的
文件頁(yè)數(shù): 3/12頁(yè)
文件大?。?/td> 88K
代理商: 24LC04
1996 Microchip Technology Inc.
DS21051E-page 3
24LC04B/08B
TABLE 1-3:
AC CHARACTERISTICS
FIGURE 1-2:
BUS TIMING DATA
Parameter
Symbol
STANDARD
MODE
V
CC
FAST MODE
= 4.5 - 5.5V
Units
Remarks
Min
Max
Min
Max
Clock frequency
Clock high time
Clock low time
SDA and SCL rise time
SDA and SCL fall time
START condition hold time
F
T
T
CLK
100
1000
300
600
1300
600
400
300
300
kHz
ns
ns
ns
ns
ns
HIGH
4000
4700
4000
LOW
T
R
T
F
:
STA
(Note 1)
(Note 1)
After this period the first clock
pulse is generated
Only relevant for repeated
START condition
T
HD
START condition setup time
T
SU
:
STA
4700
600
ns
Data input hold time
Data input setup time
STOP condition setup time
Output valid from clock
Bus free time
T
T
T
HD
:
:
:
DAT
0
0
900
ns
ns
ns
ns
ns
SU
DAT
250
4000
4700
100
600
1300
SU
T
T
STO
AA
3500
(Note 2)
Time the bus must be free
before a new transmission can
start
(Note 1), C
B
100 pF
BUF
Output fall time from V
to V
IL
max
Input filter spike suppression
(SDA and SCL pins)
Write cycle time
Endurance
IH
min
T
OF
250
20 +0.1
C
B
250
ns
T
SP
50
50
ns
(Note 3)
T
WR
10
10
ms
Byte or Page mode
cycles
25
°
C, Vcc = 5.0V, Block Mode
(Note 4)
24LC04B
24LC08B
10M
1M
10M
1M
Note 1: Not 100% tested. C
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
3: The combined T
SP
and V
HYS
specifications are due to new Schmitt trigger inputs which provide improved
noise and spike suppression. This eliminates the need for a Ti specification for standard operation.
4: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific appli-
cation, please consult the Total Endurance Model whcih can be obtained on our BBS or website.
B
= total capacitance of one bus line in pF.
T
SU
:
STA
T
F
T
LOW
T
HIGH
T
R
T
HD
:
DAT
T
SU
:
DAT
T
SU
:
STO
T
HD
:
STA
T
BUF
T
AA
T
AA
T
SP
T
HD
:
STA
SCL
SDA
IN
SDA
OUT
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