參數(shù)資料
型號: 24LC04B
廠商: Microchip Technology Inc.
英文描述: 4K/8K 2.5V I 2 C Serial EEPROMs
中文描述: 4K/8K 2.5VI 2 C串行EEPROM的
文件頁數(shù): 7/12頁
文件大小: 88K
代理商: 24LC04B
1996 Microchip Technology Inc.
DS21051E-page 7
24LC04B/08B
FIGURE 7-1:
CURRENT ADDRESS READ
FIGURE 7-2:
RANDOM READ
FIGURE 7-3:
SEQUENTIAL READ
S
P
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
S
T
A
R
T
S
T
O
P
CONTROL
BYTE
DATA n
A
C
K
N
O
A
C
K
S
P
S
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
S
T
A
R
T
S
T
O
P
CONTROL
BYTE
A
C
K
WORD
ADDRESS (n)
CONTROL
BYTE
S
T
A
R
T
DATA (n)
A
C
K
A
C
K
N
O
A
C
K
P
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
S
T
O
P
CONTROL
BYTE
A
C
K
N
O
A
C
K
DATA n
DATA n + 1
DATA n + 2
DATA n + X
A
C
K
A
C
K
A
C
K
8.0
PIN DESCRIPTIONS
8.1
SDA Serial Address/Data Input/Output
This is a Bi-directional pin used to transfer addresses
and data into and data out of the device. It is an open
drain terminal, therefore the SDA bus requires a pullup
resistor to V
CC
(typical 10K
for 100 kHz, 1K
for 400
kHz).
For normal data transfer SDA is allowed to change only
during SCL low. Changes during SCL high are
reserved for indicating the START and STOP condi-
tions.
8.2
SCL Serial Clock
This input is used to synchronize the data transfer from
and to the device.
8.3
WP
This pin must be connected to either V
SS
or V
CC
.
If tied to V
SS
, normal memory operation is enabled
(read/write the entire memory).
If tied to V
CC
, WRITE operations are inhibited. The
entire memory will be write-protected. Read operations
are not affected.
This feature allows the user to use the 24LC04B/08B as
a serial ROM when WP is enabled (tied to V
CC
).
8.4
A0, A1, A2
These pins are not used by the 24LC04B/08B. They
may be left floating or tied to either V
SS
or V
CC
.
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