參數(shù)資料
型號(hào): 24LC16B
廠商: Microchip Technology Inc.
英文描述: 16K 2.5V CMOS Serial EEPROMs(16K位、16字節(jié)頁(yè)緩沖器、10M次擦寫(xiě)周期、有硬件寫(xiě)保護(hù)、2.5-5.5V工作、CMOS IIC串行EEPROM)
中文描述: 16K的為2.5V的CMOS串行EEPROM(16K的位,16字節(jié)頁(yè)緩沖器,1000萬(wàn)次擦寫(xiě)周期,有硬件寫(xiě)保護(hù),2.5 - 5 .5 V工作,國(guó)際進(jìn)口證的CMOS串行EEPROM的)
文件頁(yè)數(shù): 5/10頁(yè)
文件大?。?/td> 111K
代理商: 24LC16B
1995 Microchip Technology Inc.
DS20070F-page 5
24LC16B
4.0
BUS CHARACTERISTICS
4.1
Device Addressing and Operation
A control byte is the first byte received following the
start condition from the master device. The control
byte consists of a four bit control code, for the 24LC16B
this is set as 1010 binary for read and write operations.
The next three bits of the control byte are the block
select bits (B2, B1, B0). They are used by the master
device to select which of the eight 256 word blocks of
memory are to be accessed. These bits are in effect
the three most significant bits of the word address. It
should be noted that the protocol limits the size of the
memory to eight blocks of 256 words, therefore the pro-
tocol can support only one 24LC16B per system.
The last bit of the control byte defines the operation to
be performed. When set to one a read operation is
selected, when set to zero a write operation is selected.
Following the start condition, the 24LC16B monitors
the SDA bus checking the device type identifier being
transmitted, upon a 1010 code the slave device outputs
an acknowledge signal on the SDA line. Depending on
the state of the R/W bit, the 24LC16B will select a read
or write operation.
FIGURE 4-1:
CONTROL BYTE
ALLOCATION
Operation
Control
Code
Block Select
R/W
Read
1010
Block Address
1
Write
1010
Block Address
0
START
READ/WRITE
SLAVE ADDRESS
R/W
1
0
1
0
B2
B1
B0
A
5.0
WRITE OPERATION
5.1
Byte Write
Following the start condition from the master, the
device code (4 bits), the block address (3 bits), and the
R/W bit which is a logic low is placed onto the bus by
the master transmitter. This indicates to the addressed
slave receiver that a byte with a word address will fol-
low after it has generated an acknowledge bit during
the ninth clock cycle. Therefore the next byte transmit-
ted by the master is the word address and will be writ-
ten into the address pointer of the 24LC16B. After
receiving another acknowledge signal from the
24LC16B the master device will transmit the data word
to be written into the addressed memory location. The
24LC16B acknowledges again and the master gener-
ates a stop condition. This initiates the internal write
cycle, and during this time the 24LC16B will not gener-
ate acknowledge signals (see Figure 5-1).
5.2
Page Write
The write control byte, word address and the first data
byte are transmitted to the 24LC16B in the same way
as in a byte write. But instead of generating a stop con-
dition the master transmits up to sixteen data bytes to
the 24LC16B which are temporarily stored in the on-
chip page buffer and will be written into the memory
after the master has transmitted a stop condition. After
the receipt of each word, the four lower order address
pointer bits are internally incremented by one. The
higher order seven bits of the word address remains
constant. If the master should transmit more than six-
teen words prior to generating the stop condition, the
address counter will roll over and the previously
received data will be overwritten. As with the byte write
operation, once the stop condition is received an inter-
nal write cycle will begin (see Figure 8-1).
FIGURE 5-1:
BYTE WRITE
S
T
O
P
SDA LINE
P
DATA
S
T
A
R
T
CONTROL
BYTE
S
WORD
ADDRESS
BUS ACTIVITY:
MASTER
BUS ACTIVITY:
A
C
K
A
C
K
A
C
K
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