- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄371399 > 24LC41A High-Speed Secure Microcontroller PDF資料下載
參數(shù)資料
| 型號： | 24LC41A |
| 英文描述： | High-Speed Secure Microcontroller |
| 中文描述： | 24LC41A數(shù)據(jù)表 |
| 文件頁數(shù)： | 3/18頁 |
| 文件大?。?/td> | 244K |
| 代理商： | 24LC41A |
2003 Microchip Technology Inc.
DS21176D-page 3
24LC41A
TABLE 1-2:
AC CHARACTERISTICS (DDC MONITOR AND MICROCONTROLLER ACCESS PORTS)
DDC Monitor Port (Bidirectional mode) and Microcontroller Access Port
Parameter
Symbol
Standard Mode
Vcc = 4.5 - 5.5V
Fast Mode
Units
Remarks
Min
—
Max
100
Min
—
Max
400
Clock frequency (DSCL and
MSCL)
Clock high time (DSCL and
MSCL)
Clock low time (DSCL and
MSCL)
DSCL, DSDA, MSCL &
MSDA rise time
DSCL, DSDA, MSCL &
MSDA fall time
Start condition hold time
F
CLK
kHz
T
HIGH
4000
—
600
—
ns
T
LOW
4700
—
1300
—
ns
T
R
—
1000
—
300
ns
(Note 1)
T
F
—
300
—
300
ns
(Note 1)
T
HD
:
STA
4000
—
600
—
ns
After this period the first clock
pulse is generated
Only relevant for repeated
Start condition
(Note 2)
Start condition setup time
T
SU
:
STA
4700
—
600
—
ns
Data input hold time
Data input setup time
Stop condition setup time
Output valid from clock
Bus free time
T
HD
:
DAT
T
SU
:
DAT
T
SU
:
STO
T
AA
T
BUF
0
—
—
—
0
—
—
—
900
—
ns
ns
ns
ns
ns
250
4000
—
4700
100
600
—
1300
3500
—
(Note 2)
Time the bus must be free
before a new transmission
can start
(Note 1)
, C
B
≤
100 pF
Output fall time from V
IH
min to V
IL
max
Input filter spike suppres-
sion (DSCL, DSDA, MSCL
& MSDA pins)
Write cycle time
Endurance
T
OF
—
250
20 + .1
C
B
—
250
ns
T
SP
—
50
50
ns
(Note 3)
T
WR
—
—
1M
10
—
—
1M
10
—
ms
Byte or Page mode
25°C, Vcc = 5.0V, Block mode
(Note 4)
cycles
DDC Monitor Port Transmit-only mode Parameters
Output valid from VCLK
VCLK high time
VCLK low time
VCLK setup time
VCLK hold time
Mode transition time
Transmit-only power-up
time
Input filter spike
suppression (VCLK pin)
Note 1:
Not 100% tested. C
B
= total capacitance of one bus line in pF.
2:
As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of DSCL or MSCL to avoid unintended generation of Start or Stop
conditions.
3:
The combined T
SP
and V
HYS
specifications are due to new Schmitt Trigger inputs which provide improved
noise and spike suppression. This eliminates the need for a T
I
specification for standard operation.
4:
This parameter is not tested but ensured by characterization. For endurance estimates in a specific
application, please consult the Total Endurance Model which can be obtained at www.microchip.com.
T
VAA
T
VHIGH
T
VLOW
T
VHST
T
SPVL
T
VHZ
T
VPU
—
2000
—
—
—
—
500
—
—
600
1300
0
600
—
0
1000
—
—
—
—
500
—
ns
ns
ns
ns
ns
ns
ns
4000
4700
0
4000
—
0
T
SPV
—
100
—
100
ns
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 24LC41A | 1K/4K 2.5V Dual Mode, Dual Port IIC Serial EEPROM(1K/4K位,雙模式雙端口，EEPROM) |
| 24LC41IP | 1K/4K 2.5V Dual Mode, Dual Port I2C⑩ Serial EEPROM |
| 24LC41P | 1K/4K 2.5V Dual Mode, Dual Port I2C⑩ Serial EEPROM |
| 24LC41 | 1K/4K 2.5V Dual Mode, Dual Port I 2 C Serial EEPROM |
| 24LC41-IP | 1K/4K 2.5V Dual Mode, Dual Port I 2 C Serial EEPROM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 24LC512/S16K | 制造商:Microchip Technology Inc 功能描述:512K, 64K X 8, 2.5V SER EE,IND - Gel-pak, waffle pack, wafer, diced wafer on film |
| 24LC512/W16K | 制造商:Microchip Technology Inc 功能描述:512K, 64K X 8, 2.5V SER EE,IND,WAFER - Gel-pak, waffle pack, wafer, diced wafer on film |
| 24LC512/WF16K | 制造商:Microchip Technology Inc 功能描述:512K, 64K X 8, 2.5V SER EE,IND - Gel-pak, waffle pack, wafer, diced wafer on film |
| 24LC512-E/MF | 功能描述:電可擦除可編程只讀存儲器 64kx8 - 2.5V RoHS:否 制造商:Atmel 存儲容量:2 Kbit 組織:256 B x 8 數(shù)據(jù)保留:100 yr 最大時鐘頻率:1000 KHz 最大工作電流:6 uA 工作電源電壓:1.7 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:SOIC-8 |
| 24LC512-E/MS | 制造商:Microchip Technology Inc 功能描述:512K, 64K X 8, 2.5V SER EE, EXT - Rail/Tube 制造商:Microchip Technology Inc 功能描述:IC EEPROM 512KBIT 400KHZ 8MSOP 制造商:Microchip Technology Inc 功能描述:512K, 64K X 8, 2.5V SER EE, EXT, 8 MSOP 3x3mm TUBE |
發(fā)布緊急采購，3分鐘左右您將得到回復。