參數(shù)資料
型號(hào)： 24LC515
廠商： Microchip Technology Inc.
英文描述： 512K I2C CMOS Serial EEPROM
中文描述： 為512k的I2C的CMOS串行EEPROM
文件頁(yè)數(shù)： 5/22頁(yè)
文件大小： 285K
代理商： 24LC515
2003 Microchip Technology Inc.
Preliminary
DS21673C-page 5
24AA515/24LC515/24FC515
2.0
PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 2-1.
TABLE 2-1:
PIN FUNCTION TABLE
2.1
A0, A1 Chip Address Inputs
The A0, A1 inputs are used by the 24XX515 for multiple
device operations. The levels on these inputs are
compared with the corresponding bits in the slave
address. The chip is selected if the compare is true.
Up to four devices may be connected to the same bus
by using different Chip Select bit combinations. If left
unconnected, these inputs will be pulled down
internally to V
SS
.
2.2
A2 Chip Address Input
The A2 input is non-configurable Chip Select. This pin
must be tied to V
CC
in order for this device to operate.
2.3
Serial Data (SDA)
This is a bidirectional pin used to transfer addresses
and data into and data out of the device. It is an open-
drain terminal, therefore, the SDA bus requires a pull-
up resistor to V
CC
(typical 10 k
for 100 kHz, 2 k
for
400 kHz and 1 MHz).
For normal data transfer SDA is allowed to change only
during SCL low. Changes during SCL high are
reserved for indicating the Start and Stop conditions.
2.4
Serial Clock (SCL)
This input is used to synchronize the data transfer from
and to the device.
2.5
Write-Protect (WP)
This pin can be connected to either V
SS
, V
CC
or left
floating. An internal pull-down resistor on this pin will
keep this device in the unprotected state if left floating.
If tied to V
SS
or left floating, normal memory operation
is enabled (read/write the entire memory 0000h-
FFFFh).
If tied to V
CC
, write operations are inhibited. Read
operations are not affected.
3.0
FUNCTIONAL DESCRIPTION
The 24XX515 supports a bidirectional 2-wire bus and
data transmission protocol. A device that sends data
onto the bus is defined as a transmitter, and a device
receiving data as a receiver. The bus must be
controlled by a master device which generates the
serial clock (SCL), controls the bus access, and
generates the Start and Stop conditions while the
24XX515 works as a slave. Both master and slave can
operate as a transmitter or receiver, but the master
device determines which mode is activated.
Name PDIP SOIC
Function
A0
A1
A2
1
2
3
1
2
3
User Configurable Chip Select
User Configurable Chip Select
Non-Configurable Chip Select.
This pin must be hard wired to
logical 1 state (V
CC
). Device
will not operate with this pin
left floating or held to logical 0
(V
SS
).
Ground
Serial Data
Serial Clock
Write-Protect Input
+1.8 to 5.5V (24AA515)
+2.5 to 5.5V (24LC515)
+4.5 to 5.5V (24FC515)
V
SS
SDA
SCL
WP
V
CC
4
5
6
7
8
4
5
6
7
8
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