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| 型號： | 25759 |
| 英文描述： | Revision Guide for AMD Athlon 64? and AMD Opteron? Processors |
| 中文描述： | 修訂指南的AMD Athlon 64？和AMD Opteron？處理器 |
| 文件頁數(shù)： | 7/49頁 |
| 文件大?。?/td> | 287K |
| 代理商： | 25759 |
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Product Errata
7
Revision Guide for AMD Athlon 64 and AMD Opteron Processors
25759
Rev. 3.09
September 2003
Product Errata
This section documents product errata for the processors. A unique tracking number for each erratum
has been assigned within this document for user convenience in tracking the errata within specific
revision levels. Table 2 cross-references the revisions of the part to each erratum. An “X” indicates
that the erratum applies to the revision. The absence of an “X” indicates that the erratum does not
apply to the revision. An “
*
” indicates advance information that the erratum has been fixed but not yet
verified. “No fix planned” indicates that no fix is planned for current or future revisions of the
processor.
Note:
There may be missing errata numbers. Errata that have been resolved from early revisions of
the processor have been deleted, and errata that have been reconsidered may have been
deleted or renumbered.
Table 2.
Cross-Reference of Product Revision to Errata
No.
Errata Description
Revision Number
S
S
1
51
57
58
60
61
62
63
64
65
66
68
69
71
74
75
76
77
Inconsistent Global Page Mappings Can Lead to Machine Check Error
Arbitrated Interrupt With Illegal Vector Sets APIC Error Bit In All Processors
Some Data Cache Tag Eviction Errors Are Reported As Snoop Errors
Memory Latency with Processor Power States
Single Machine Check Error May Report Overflow
Real Mode RDPMC with Illegal ECX May Cause Unpredictable Operation
Task Gates With Breakpoints Enabled May Cause Unexpected Faults
TLB Flush Filter Causes Coherency Problem in Multiprocessor Systems
Single Step Across I/O SMI Skips One Debug Trap
Uncorrectable NB Machine Check Error May Disrupt Power Management
Upstream Read Response Delayed by Downstream Posted Writes
Disable DQS Hysteresis Bit Not Readable
Multiprocessor Coherency Problem with Hardware Prefetch Mechanism
RSM from SMM with Paging Enabled May Deadlock
Registered DIMM Exit-Self-Refresh Requirements Not Met
APIC Timer Accuracy Across Power Management Events
APIC Timer Undercounts In Divide-by-8 Low Power Mode
Long Mode CALLF or JMPF May Fail To Signal GP When Callgate Descriptor
is Beyond GDT/LDT Limit
No fix planned
X
No fix planned
X
No fix planned
X
X
X
X
X
X
X
X
X
X
No fix planned
X
No fix planned
X
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