參數(shù)資料
型號(hào): 25AA020A
廠商: Microchip Technology Inc.
英文描述: 2K SPI Bus Serial EEPROM
中文描述: 2K SPI總線串行EEPROM
文件頁(yè)數(shù): 11/28頁(yè)
文件大小: 362K
代理商: 25AA020A
2006 Microchip Technology Inc.
Preliminary
DS21833C-page 11
25AA020A/25LC020A
2.6
Write Status Register Instruction
(
WRSR
)
The Write Status Register instruction (
WRSR
) allows
the user to write to the nonvolatile bits in the STATUS
register as shown in Table 2-2. See Figure 2-7 for the
WRSR
timing sequence. Four levels of protection for
the array are selectable by writing to the appropriate
bits in the STATUS register. The user has the ability to
write-protect none, one, two, or all four of the
segments of the array as shown in Table 2-3.
TABLE 2-3:
ARRAY PROTECTION
FIGURE 2-7:
WRITE STATUS REGISTER TIMING SEQUENCE (
WRSR
)
BP1
BP0
Array Addresses
Write-Protected
0
0
0
1
none
upper 1/4
(C0h-FFh)
upper 1/2
(80h-FFh)
all
(00h-FFh)
1
0
1
1
SO
SI
CS
9
10
11
12
13
14
15
0
1
0
0
0
0
0
0
7
6
5
4
2
1
0
instruction
data to STATUS register
high-impedance
SCK
0
2
3
4
5
6
7
1
8
3
Note:
An internal write cycle (T
WC
) is initiated on the rising edge of CS after a valid write STATUS register
sequence.
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