參數(shù)資料
型號(hào)： 25AA020A
廠商： Microchip Technology Inc.
英文描述： 2K SPI Bus Serial EEPROM
中文描述： 2K SPI總線串行EEPROM
文件頁(yè)數(shù)： 6/28頁(yè)
文件大?。?/td> 362K
代理商： 25AA020A
25AA020A/25LC020A
DS21833C-page 6
Preliminary
2006 Microchip Technology Inc.
2.0
FUNCTIONAL DESCRIPTION
2.1
Principles of Operation
The 25XX020A is a 256-byte Serial EEPROM
designed to interface directly with the Serial Peripheral
Interface (SPI) port of many of today’s popular
microcontroller
families,
PICmicro
microcontrollers. It may also interface with
microcontrollers that do not have a built-in SPI port by
using discrete I/O lines programmed properly in
software to match the SPI protocol.
The 25XX020A contains an 8-bit instruction register.
The device is accessed via the SI pin, with data being
clocked in on the rising edge of SCK. The CS pin must
be low and the HOLD pin must be high for the entire
operation.
Table 2-1 contains a list of the possible instruction
bytes and format for device operation. All instructions,
addresses, and data are transferred MSb first, LSb last.
Data (SI) is sampled on the first rising edge of SCK
after CS goes low. If the clock line is shared with other
peripheral devices on the SPI bus, the user can assert
the HOLD input and place the 25XX020A in ‘HOLD’
mode. After releasing the HOLD pin, operation will
resume from the point when the HOLD was asserted.
including
Microchip’s
2.2
Read Sequence
The device is selected by pulling CS low. The 8-bit
READ
instruction is transmitted to the 25XX020A fol-
lowed by an 8-bit address. See Figure 2-1 for more
details.
After the correct
READ
instruction and address are sent,
the data stored in the memory at the selected address
is shifted out on the SO pin. Data stored in the memory
at the next address can be read sequentially by
continuing to provide clock pulses to the slave. The
internal Address Pointer automatically increments to
the next higher address after each byte of data is
shifted out. When the highest address is reached
(FFh), the address counter rolls over to address 00h
allowing the read cycle to be continued indefinitely. The
read operation is terminated by raising the CS pin
(Figure 2-1).
2.3
Write Sequence
Prior to any attempt to write data to the 25XX020A, the
write enable latch must be set by issuing the
WREN
instruction (Figure 2-4). This is done by setting CS low
and then clocking out the proper instruction into the
25XX020A. After all eight bits of the instruction are
transmitted, CS must be driven high to set the write
enable latch. If the write operation is initiated immedi-
ately after the
WREN
instruction without CS driven high,
data will not be written to the array since the write
enable latch was not properly set.
After setting the write enable latch, the user may
proceed by driving CS low, issuing a
WRITE
instruction,
followed by the remainder of the address, and then the
data to be written. Up to 16 bytes of data can be sent to
the device before a write cycle is necessary. The only
restriction is that all of the bytes must reside in the
same page. Additionally, a page address begins with
XXXX 0000
and ends with
XXXX 1111
. If the internal
address counter reaches
XXXX 1111
and clock signals
continue to be applied to the chip, the address counter
will roll back to the first address of the page and over-
write any data that previously existed in those
locations.
For the data to be actually written to the array, the CS
must be brought high after the Least Significant bit (D0)
of the
n
th
data byte has been clocked in. If CS is driven
high at any other time, the write operation will not be
completed. Refer to Figure 2-2 and Figure 2-3 for more
detailed illustrations on the byte write sequence and
the page write sequence respectively. While the write is
in progress, the STATUS register may be read to check
the status of the WIP, WEL, BP1 and BP0 bits
(Figure 2-6). Attempting to read a memory array
location will not be possible during a write cycle. Polling
the WIP bit in the STATUS register is recommended in
order to determine if a write cycle is in progress. When
the write cycle is completed, the write enable latch is
reset.
Note:
Page write operations are limited to writing
bytes within a single physical page,
regardless
of the number of bytes
actually being written. Physical page
boundaries start at addresses that are
integer multiples of the page buffer size (or
‘page size’) and, end at addresses that are
integer multiples of page size – 1. If a
Page Write command attempts to write
across a physical page boundary, the
result is that the data wraps around to the
beginning of the current page (overwriting
data previously stored there), instead of
being written to the next page as might be
expected. It is therefore necessary for the
application software to prevent page write
operations that would attempt to cross a
page boundary.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
25AA020A/S16K 功能描述:電可擦除可編程只讀存儲(chǔ)器 2K, 256 X 8, 1.8V SER EE, DIE in WAFFLE PK RoHS:否 制造商:Atmel 存儲(chǔ)容量:2 Kbit 組織:256 B x 8 數(shù)據(jù)保留:100 yr 最大時(shí)鐘頻率:1000 KHz 最大工作電流:6 uA 工作電源電壓:1.7 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-8
25AA020A/W16K 功能描述:電可擦除可編程只讀存儲(chǔ)器 2K, 256 X 8, 1.8V SER EE, WAFER RoHS:否 制造商:Atmel 存儲(chǔ)容量:2 Kbit 組織:256 B x 8 數(shù)據(jù)保留:100 yr 最大時(shí)鐘頻率:1000 KHz 最大工作電流:6 uA 工作電源電壓:1.7 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-8
25AA020A/WF16K 功能描述:電可擦除可編程只讀存儲(chǔ)器 2K, 256 X 8, 1.8V SER EE, WAFER on FRAME RoHS:否 制造商:Atmel 存儲(chǔ)容量:2 Kbit 組織:256 B x 8 數(shù)據(jù)保留:100 yr 最大時(shí)鐘頻率:1000 KHz 最大工作電流:6 uA 工作電源電壓:1.7 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-8
25AA020A_12 制造商:MICROCHIP 制造商全稱:Microchip Technology 功能描述:2K SPI Bus Serial EEPROM
25AA020A-E/MC 制造商:MICROCHIP 制造商全稱:Microchip Technology 功能描述:2K SPI Bus Serial EEPROM
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