參數(shù)資料
型號： 25LC128
廠商： Microchip Technology Inc.
英文描述： 128K 5.0V SPI Bus Serial EEPROM(2.5~5.5V,128K位,SPI總線串行EEPROM)
中文描述： 128K的5.0V SPI總線串行EEPROM（2.5?5.5V的，128K的位和SPI總線串行EEPROM的）
文件頁數(shù)： 62/170頁
文件大小： 4191K
代理商： 25LC128
PIC16F62X
DS40300C-page 60
Preliminary
2003 Microchip Technology Inc.
EXAMPLE 10-1:
VOLTAGE REFERENCE
CONFIGURATION
10.2
Voltage Reference Accuracy/Error
The full range of V
SS
to V
DD
cannot be realized due to
the construction of the module. The transistors on the
top and bottom of the resistor ladder network
(Figure 10-1) keep V
REF
from approaching V
SS
or V
DD
.
The Voltage Reference is V
DD
derived and therefore,
the V
REF
output changes with fluctuations in V
DD
. The
tested absolute accuracy of the Voltage Reference can
be found in Table 17-2.
10.3
Operation During SLEEP
When the device wakes-up from SLEEP through an
interrupt or a Watchdog Timer timeout, the contents of
the VRCON register are not affected. To minimize
current consumption in SLEEP mode, the Voltage
Reference should be disabled.
10.4
Effects of a RESET
A device RESET disables the Voltage Reference by
clearing bit V
REN
(VRCON<7>). This RESET also
disconnects the reference from the RA2 pin by clearing
bit V
ROE
(VRCON<6>) and selects the high voltage
range by clearing bit V
RR
(VRCON<5>). The V
REF
value select bits, VRCON<3:0>, are also cleared.
10.5
Connection Considerations
The
independently of the Comparator module. The output
of the reference generator may be connected to the
RA2 pin if the TRISA<2> bit is set and the V
ROE
bit,
VRCON<6>, is set. Enabling the Voltage Reference
output onto the RA2 pin with an input signal present will
increase current consumption. Connecting RA2 as a
digital output with V
REF
enabled will also increase
current consumption.
Voltage
Reference
module
operates
The RA2 pin can be used as a simple D/A output with
limited drive capability. Due to the limited drive
capability, a buffer must be used in conjunction with the
Voltage Reference output for external connections to
V
REF
. Figure 10-2 shows an example buffering
technique.
FIGURE 10-2:
VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE
TABLE 10-1:
REGISTERS ASSOCIATED WITH VOLTAGE REFERENCE
MOVLW
MOVWF
BSF
MOVLW
MOVWF
MOVLW
MOVWF
0x02
CMCON
STATUS,RP0
0x07
TRISA
0xA6
VRCON
; 4 Inputs Muxed
; to 2 comps.
; go to Bank 1
; RA3-RA0 are
; outputs
; enable V
REF
; low range
; set V
R
<3:0>=6
; go to Bank 0
; 10
μ
s delay
BCF
CALL
STATUS,RP0
DELAY10
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value On
POR
Value On
All Other
RESETS
9Fh
VRCON
VREN
VROE
VRR
—
VR3
VR2
VR1
VR0
000- 0000
000- 0000
1Fh
CMCON
C2OUT
C1OUT
C2INV
C1INV
CIS
CM2
CM1
CM0
0000 0000
0000 0000
85h
TRISA
TRISA7 TRISA6 TRISA5
TRISA4
TRISA3
TRISA2
TRISA1
TRISA0
1111 1111
1111 1111
Note 1:
— = Unimplemented, read as ‘0’.
Note
1:
R is dependent upon the Voltage Reference Configuration VRCON<3:0> and VRCON<5>.
V
REF
Module
R
(1)
Voltage
Reference
Output
Impedance
RA2
V
REF
Output
+
Op Amp
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