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| 型號： | 27174A |
| 英文描述： | Versatile I/0: DQ--VI/O and Enhanced--VI/O |
| 中文描述： | 通用的I / 0：宿舍-六/ O和增強-六/輸出 |
| 文件頁數(shù)： | 2/4頁 |
| 文件大?。?/td> | 67K |
| 代理商： | 27174A |
Publication#
27174
Issue Date:
October 23, 2002
Rev:
A
Amendment/
0
Versatile I/O: DQ
–
V
I/O
and Enhanced
–
V
I/O
Application Note
This document describes the two types of Versatile I/O
provided by AMD Flash memory: DQ-V
I/O
and En-
hanced-V
I/O
. Also described are the benefits of
designing with AMD’s Versatile I/O Flash memory in
terms of reducing system complexity, and the limita-
tions of each type of Versatile I/O interface.
What is Versatile I/O (V
I/O
)
Versatile I/O (V
I/O
) is used on AMD Flash memory to
provide support for I/O signaling that is outside the
“normal” operating range of a device. Versatile I/O al-
lows a 3.0V AMD Flash to be compatible with 2.5V or
1.8V devices without the need of expensive voltage
translation buffers, as shown in Figure 1. Also, Versa-
tile I/O enables this without affecting the overall
performance of the Flash device.
Figure 1.
I/O Signaling to Typical 3V Flash
Versatile I/O devices can provide this internal voltage
conversion because unlike traditional Flash memory,
where a single power supply (V
CC
) is used to power
both the memory array and I/O pins, V
CC
only powers
the memory array while the V
I/O
pin(s) power the I/O
pins. This allows a Versatile I/O Flash device to directly
interface with a wide variety of FPGAs, ASICs, micro-
processors, microcontrollers, and other digital devices
regardless of the device operating voltage. For exam-
ple if a board is using a 3.0V AMD Flash, and a 1.8V
microcontroller. A typical Flash would have problems
since the typical minimum legal high for a 3.0V device
is 2.1V (3.0V * 0.7 = 2.1V), this is higher than the
source voltage of the 1.8V microcontroller. With AMD’s
Versatile I/O Flash memory the V
I/O
pin(s) would be
connected to the 1.8V source used by the microcontrol-
ler, making the voltage levels for the inputs and outputs
JEDEC 1.8V compliant.
System Performance
The performance of the system shown in Figure 1 is
also greatly affected because of the need for transla-
tion buffers. The buffers consume up to 100 mA of
current each and data skew will occur any time a signal
passes through the buffers. This data skew is due to vari-
ations in the propagation delay between parts and also
between the individual pins on a buffer. However, the
skew between individual pins is typically much smaller
than between individual buffer chips.
The propagation delays through voltage translation
buffers are highly variable, on the order of 2 ns to 7 ns,
and discrepant on bi-directional buffers. In Figure 1,
MicroController
Vcc = 1.8v
Address
Data
Control
x8
x16
x24
Typical 3v
Flash
Other 1.8v
Devices
32
16
8
Voltage
Translation
Buffers
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