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參數(shù)資料
| 型號： | 27174A |
| 英文描述： | Versatile I/0: DQ--VI/O and Enhanced--VI/O |
| 中文描述： | 通用的I / 0：宿舍-六/ O和增強(qiáng)-六/輸出 |
| 文件頁數(shù)： | 3/4頁 |
| 文件大?。?/td> | 67K |
| 代理商： | 27174A |
Versatile I/O: DQ–V
I/O
and Enhanced–V
I/O
there could be as much as a 5 ns delay between a con-
trol or clock signal and the data and address signals.
This delay may also occur between the upper and
lower address and/or data lines. To put this in perspec-
tive, if the Flash used in Figure 1 is a 66 MHz Flash, it
could not be safely used at speeds above 50 MHz due
to the uncertainty in the translation buffers’ propagation
delay.
DQ
–
Versatile I/O (DQ
–
V
I/O
)
AMD’s DQ based Versatile I/O (DQ–V
I/O
) follows an old
standard for compatibility with Intel Flash devices and
other legacy devices. This standard calls for the data
pins (DQx) and chip enable (CE#) to be compatible
with the Versatile I/O voltage while all other pins (Ad-
dress, OE#, RY/BY#, etc) still require signaling at V
CC
voltage levels.
Figure 2.
I/O Signaling to DQ–V
IO
3V Flash with V
IO
= 1.8V
Therefore, as shown in Figure 2, only the data lines and
chip select signals from the microcontroller and Flash
can be connected together directly. The address lines,
OE#, WE#, RESET#, RY/BY#, BYTE#, etc. would
have to pass through voltage translation buffers in
order for the Flash to receive legal high values and to
prevent the microcontroller from being damaged by
3.0V signals from the Flash.
AMD’s DQ–Versatile I/O may at first seem to be of lim-
ited use since only one 16-bit voltage translator is
saved but this small change can greatly increase sys-
tem performance. AMD’s DQ–V
I/O
parts were designed
on the assumption that most high-speed microproces-
sors will assert the address and control lines before
asserting the data lines. By removing the need for volt-
age translation buffers on the data lines and assuming
the address and control lines are asserted half a clock
cycle before the data lines, the clock rate can be in-
creased from 50 MHz to 66 MHz.
Enhanced
–
Versatile I/O (Enhanced
–
V
I/O
)
AMD’s Enhanced–Versatile I/O is similar to the DQ–V
I/
O
, but with the added benefit of having all input and out-
put pins being compatible with the Versatile I/O voltage
and only the internal core memory and logic operating
at the V
CC
voltage.
MicroController
Vcc = 1.8v
Address
Data
Control
x7
x24
DQ-V
I/O
3v
Flash
with V
I/O
= 1.8v
Voltage
Translation
Buffers
Other 1.8v
Devices
32
16
8
16
C
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