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參數(shù)資料
| 型號(hào)： | 27C256-12L |
| 廠商： | Microchip Technology Inc. |
| 英文描述： | 256K (32K x 8) CMOS EPROM |
| 中文描述： | 256K（32K的× 8）的CMOS存儲(chǔ)器 |
| 文件頁(yè)數(shù)： | 5/12頁(yè) |
| 文件大?。?/td> | 67K |
| 代理商： | 27C256-12L |
1996 Microchip Technology Inc.
DS11001L-page 5
27C256
FIGURE 1-2:
PROGRAMMING WAVEFORMS
TABLE 1-6:
MODES
Operation Mode
CE
OE
V
PP
A9
O0 - O7
Read
Program
Program Verify
Program Inhibit
Standby
Output Disable
Identity
V
IL
V
IL
V
IH
V
IH
V
IH
V
IL
V
IL
V
IL
V
IH
V
IL
V
IH
X
V
IH
V
IL
V
CC
V
H
V
H
V
H
V
CC
V
CC
V
CC
X
X
X
X
X
X
V
H
D
OUT
D
IN
D
OUT
High Z
High Z
High Z
Identity Code
X = Don’t Care
V
IH
V
IL
V
IH
V
IL
13.0V(2)
5.0V
6.5V(2)
5.0V
V
IH
V
IL
V
IH
V
IL
Address
Data
V
PP
V
CC
CE
OE
t
DF
and t
OE
are characteristics of the device but must be accommodated by the programmer
V
CC
= 6.5 V
±
0.25V, V
PP
= V
H
= 13.0V
±
0.25V for express algorithm
t
PW
t
OES
Address Stable
t
AH
t
DS
t
VPS
t
DF
(1)
t
DH
t
OE
(1)
t
AS
Program
Data Stable
Data Out Valid
Verify
t
VCS
Notes:
(1)
(2)
High Z
1.2
Read Mode
(See Timing Diagrams and AC Characteristics)
Read Mode is accessed when:
a)
the CE pin is low to power up (enable) the chip
b)
the OE pin is low to gate the data to the output
pins
For Read operations, if the addresses are stable, the
address access time (t
ACC
) is equal to the delay from
CE to output (t
CE
). Data is transferred to the output
after a delay from the falling edge of OE (t
OE
).
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| 27C256-12P | 256K (32K x 8) CMOS EPROM |
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| 27C256-12VS | 256K (32K x 8) CMOS EPROM |
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| 27C256-12N | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:256K-bit CMOS EPROM (32K x 8) |
| 27C256-12P | 制造商:MICROCHIP 制造商全稱:Microchip Technology 功能描述:256K (32K x 8) CMOS EPROM |
| 27C256-12SO | 制造商:MICROCHIP 制造商全稱:Microchip Technology 功能描述:256K (32K x 8) CMOS EPROM |
| 27C256-12TS | 制造商:MICROCHIP 制造商全稱:Microchip Technology 功能描述:256K (32K x 8) CMOS EPROM |
| 27C256-12VS | 制造商:MICROCHIP 制造商全稱:Microchip Technology 功能描述:256K (32K x 8) CMOS EPROM |
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