
192
11.0 PCI Bus Interface
11.4 Burst FIFO Buffers
RS8234
Datasheet for RS8234 xBR ServiceSAR
N8234DS1B
tion space will be set and the PCI_BUS_STATUS[1] bit in the SYS_STAT
Register will be set.
5
Internal Failure—Upon a synchronization error between the DMA copro-
cessor and the PCI master logic, an internal failure will be flagged. In this
case, the MERROR and INT_FAIL bits in the PCI configuration space will
be set and the PCI_BUS_STATUS[0] bit in the SYS_STAT Register will
be set.
* The above errors permanently affect system level operation. Because of this
the system should be re-initialized, since full system level recovery is unlikely.
The bus protocol errors can be cleared either by a software reset of the associated
status flag or flags, i.e., RTA, RMA, or DPR, or with a reset of the PCI bus master
logic using the HRST* input pin. For example, a master abort error can be cleared
by writing a logic one to the RMA status bit in the PCI Configuration Register
space, causing the status bit to be cleared. Internal failures (attempting to initiate
a master transaction with the interface disabled, or loss of synchronization with
the DMA controller) can only be reset by applying the global reset,
CONFIG0(GLOBAL_RESET), or by asserting the HRST* signal.
Next, the MERROR bit must be cleared. The MERROR bit in the PCI Config-
uration Register drives the PCI_BUS_ERROR interrupt. To clear this interrupt, a
logic high must be written to the MERROR bit location. The MERROR bit can
also be cleared by a logic low on the HRST* input pin.
* The local processor can clear the error bits by setting CONFIG0
(PCI_ERR_RESET) to a logic high. After the errors have been cleared, the SAR
should be re-initialized.
Several fields are provided in the PCI configuration space to aid in recovering
from a PCI master error. The PCI host software can determine that an error
occurred by checking the MERROR bit. It also can determine if the transaction
was a read or write by inspecting the MRD bit, and the read or write address at
which an error occurred by reading the MASTER_READ_ADDR or
MASTER_WRITE_ADDR fields.
The PCI Read and PCI Read MULTIPLE commands issued by the PCI block
are under the control of the PCI_READ_MULTI bit in the CONFIG0 register.
11.4 Burst FIFO Buffers
Two small FIFO buffers are implemented to support PCI burst-mode operation, to
allow synchronization between the RS8234 internal logic and the PCI bus inter-
face, and to carry commands from the DMA coprocessor to the PCI bus logic.
The incoming FIFO is 512 x 32 bits, the outgoing FIFO is 16 x 36 bits.
11.5 PCI Bus Slave Logic
The PCI slave logic permits the host CPU on the PCI bus to access and modify
RS8234 resources (the external SAR shared memory, internal memory, and inter-
nal registers). As the control processor also has access to these resources, the PCI