- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄371435 > 28F160C2 (Intel Corp.) 2.4V Advanced+ Boot Block Flash Memory(2.4V高級引導(dǎo)塊閃速存儲(chǔ)器) PDF資料下載
參數(shù)資料
| 型號： | 28F160C2 |
| 廠商： | Intel Corp. |
| 英文描述： | 2.4V Advanced+ Boot Block Flash Memory(2.4V高級引導(dǎo)塊閃速存儲(chǔ)器) |
| 中文描述： | 2.4V的高級啟動(dòng)塊閃存（2.4V的高級引導(dǎo)塊閃速存儲(chǔ)器） |
| 文件頁數(shù)： | 23/56頁 |
| 文件大?。?/td> | 283K |
| 代理商： | 28F160C2 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁當(dāng)前第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁
E
System engineers should analyze the breakdown of
standby time versus active time and quantify the
respective power consumption in each mode for
their specific application. This will provide a more
accurate measure of application-specific power and
energy requirements.
28F800C2, 28F160C2
23
PRELIMINARY
3.6.4
DEEP POWER-DOWN MODE
The deep power-down mode is activated when
RP#
=
V
IL
(GND
±
0.2 V). During read modes, RP#
going low de-selects the memory and places the
outputs in a high impedance state. Recovery from
deep power-down requires a minimum time of t
PHQV
for read operations and t
PHWL
/t
PHEL
for write
operations.
During program or erase modes, RP# transitioning
low will abort the in-progress operation. The
memory contents of the address being programmed
or the block being erased are no longer valid as the
data integrity has been compromised by the abort.
During deep power-down, all internal circuits are
switched to a low power savings mode (RP#
transitioning to V
IL
or turning off power to the device
clears the status register).
3.7
Power-Up/Down Operation
The device is protected against accidental block
erasure or programming during power transitions.
Power supply sequencing is not required, since
the
device is indifferent as to which power supply, V
PP
or V
CC
, powers-up first.
3.7.1
RP# CONNECTED TO SYSTEM
RESET
The use of RP# during system reset is important
with automated program/erase devices since the
system expects to read from the flash memory
when it comes out of reset. If a CPU reset occurs
without a flash memory reset, proper CPU
initialization will not occur because the flash
memory may be providing status information
instead of array data. Intel recommends connecting
RP# to the system CPU RESET# signal to allow
proper CPU/flash initialization following system
reset.
System designers must guard against spurious
writes when V
CC
voltages are above V
LKO
. Since
both WE# and CE# must be low for a command
write, driving either signal to V
IH
will
inhibit writes to
the device. The CUI architecture provides additional
protection since alteration of memory contents can
only occur after successful completion of the two-
step command sequences. The device is also
disabled until RP# is brought to V
IH
, regardless of
the state of its control inputs. By holding the device
in reset (RP# connected to system PowerGood)
during power-up/down, invalid bus conditions during
power-up can be masked, providing yet another
level of memory protection.
3.7.2
V
CC
, V
PP
AND RP# TRANSITIONS
The CUI latches commands as issued by
system
software and is not altered by V
PP
or CE#
transitions or WSM actions. Its default state upon
power-up, after exit from reset mode or after V
CC
transitions above V
LKO
(Lockout voltage), is read
array mode.
After any program or block erase operation is
complete (even after V
PP
transitions down to
V
PPLK
), the CUI must be reset to read array mode
via the Read Array command if access to the flash
memory array is desired.
3.8
Power Supply Decoupling
Flash memory’s power switching characteristics
require
careful
device
designers should consider three supply current
issues:
1.
Standby current levels (I
CCS
)
2.
Read current levels (I
CCR
)
3.
Transient peaks produced by falling and rising
edges of CE#.
decoupling.
System
Transient current magnitudes depend on the device
outputs’ capacitive and inductive loading. Two-line
control and proper decoupling capacitor selection
will suppress these transient voltage peaks. Each
flash device should have a 0.1 μF ceramic
capacitor connected between each V
CC
and GND,
and between its V
PP
and GND. These high-
frequency, inherently low-inductance capacitors
should be placed as close as possible to the
package leads.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 28F800C2 | 2.4V Advanced+ Boot Block Flash Memory(2.4V高級引導(dǎo)塊閃速存儲(chǔ)器) |
| 28F160S3 | 3 V FlashFile Memory(3 V FlashFile 存儲(chǔ)器) |
| 28F320S3 | 3 V、32MB FlashFile Memory(3 V、32M位FlashFile 存儲(chǔ)器) |
| 28F160S5 | 5 V FlashFile Memory(5 V FlashFile 存儲(chǔ)器) |
| 28F320S5 | 3 V、32MB FlashFile Memory(3 V、32M位FlashFile 存儲(chǔ)器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 28F160C3 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:3 Volt Intel Advanced+ Boot Block Flash Memory |
| 28F160C3BA90 | 制造商: 功能描述: 制造商:Intel 功能描述: 制造商:undefined 功能描述: |
| 28F160C3TD70 | 制造商: 功能描述: 制造商:undefined 功能描述: |
| 28F160F3 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FAST BOOT BLOCK FLASH MEMORY FAMILY 8 AND 16 MBIT |
| 28F160F3B95 | 制造商:Intel 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。