
28F800C3, 28F160C3, 28F320C3, 28F640C3
22
3UHOLPLQDU\
By holding the device in reset (RP# connected to system PowerGood) during power-up/down,
invalid bus conditions during power-up can be masked, providing yet another level of memory
protection.
3.7.2
V
CC
, V
PP
and RP# Transitions
The CUI latches commands as issued by
system software and is not altered by V
PP
or CE#
transitions or WSM actions. Its default state upon power-up, after exit from reset mode or after
V
CC
transitions above V
LKO
(Lockout voltage), is read array mode.
After any program or block erase operation is complete (even after V
PP
transitions down to
V
PPLK
), the CUI must be reset to read array mode via the Read Array command if access to the
flash memory array is desired.
3.8
Power Supply Decoupling
Flash memory’s power switching characteristics require careful device decoupling. System
designers should consider three supply current issues:
Standby current levels (I
CCS
)
Read current levels (I
CCR
)
Transient peaks produced by falling and rising edges of CE#.
Transient current magnitudes depend on the device outputs’ capacitive and inductive loading. Two-
line control and proper decoupling capacitor selection will suppress these transient voltage peaks.
Each flash device should have a 0.1 μF ceramic capacitor connected between each V
CC
and GND,
and between its V
PP
and GND. These high- frequency, inherently low-inductance capacitors should
be placed as close as possible to the package leads.