參數(shù)資料
型號(hào)： 29F022T-70
廠商： Macronix International Co., Ltd.
英文描述： 2M-BIT[256K x 8]CMOS FLASH MEMORY
中文描述： 200萬(wàn)位[256K × 8]的CMOS閃存
文件頁(yè)數(shù)： 12/46頁(yè)
文件大小： 606K
代理商： 29F022T-70
12
P/N:PM0556
REV. 1.3, NOV. 11, 2002
MX29F022/022NT/B
Q3
Sector Erase Timer
After the completion of the initial sector erase command
sequence the sector erase time-out will begin. Q3 will
remain low until the time-out is complete. Data Polling
and Toggle Bit are valid after the initial sector erase com-
mand sequence.
If Data Polling or the Toggle Bit indicates the device has
been written with a valid erase command, Q3 may be
used to determine if the sector erase timer window is
still open. If Q3 is high ("1") the internally controlled
erase cycle has begun; attempts to write subsequent
commands to the device will be ignored until the erase
operation is completed as indicated by Data Polling or
Toggle Bit. If Q3 is low ("0"), the device will accept
additional sector erase commands. To insure the
command has been accepted, the system software
should check the status of Q3 prior to and following each
subsequent sector erase command. If Q3 were high on
the second status check, the command may not have
been accepted.
DATA PROTECTION
The MX29F022T/B is designed to offer protection against
accidental erasure or programming caused by spurious
system level signals that may exist during power transi-
tion. During power up the device automatically resets
the state machine in the Read mode. In addition, with its
control register architecture, alteration of the memory
contents only occurs after successful completion of spe-
cific command sequences. The device also incorporates
several features to prevent inadvertent write cycles re-
sulting from VCC power-up and power-down transition or
system noise.
WRITE PULSE "GLITCH" PROTECTION
Noise pulses of less than 5ns (typical) on CE or WE will
not initiate a write cycle.
LOGICAL INHIBIT
Writing is inhibited by holding any one of OE = VIL, CE =
VIH or WE = VIH. To initiate a write cycle CE and WE
must be a logical zero while OE is a logical one.
POWER SUPPLY DECOUPLING
In order to reduce power switching effect, each device
should have a 0.1uF ceramic capacitor connected be-
tween its VCC and GND.
CHIP PROTECTION WITH 12V SYSTEM
The MX29F022T/B features hardware chip protection,
which will disable both program and erase operations. To
activate this mode, the programming equipment must
force VID on address pin A9 and control pin OE, (sug-
gest VID = 12V) A6 = VIL and CE = VIL.(see Table 2)
Programming of the protection circuitry begins on the
falling edge of the WE pulse and is terminated on the
rising edge. Please refer to chip protect algorithm and
waveform.
To verify programming of the protection circuitry, the
programming equipment must force VID on address pin
A9 ( with CE and OE at VIL and WE at VIH. When A1=1,
it will produce a logical "1" code at device output Q0 for
the protected status. Otherwise the device will produce
00H for the unprotected status. In this mode, the ad-
dresses, except for A1, are in "don't care" state. Ad-
dress locations with A1 = VIL are reserved to read manu-
facturer and device codes.(Read Silicon ID)
It is also possible to determine if the chip is protected in
the system by writing a Read Silicon ID command.
Performing a read operation with A1=VIH, it will produce
a logical "1" at Q0 for the protected status.
CHIP UNPROTECT WITH 12V SYSTEM
The MX29F022T/B also features the chip unprotect mode,
so that all sectors are unprotected after chip unprotect is
completed to incorporate any changes in the code.
To activate this mode, the programming equipment must
force VID on control pin OE and address pin A9. The CE
pins must be set at VIL. Pins A6 must be set to VIH.(see
Table 2) Refer to chip unprotect algorithm and waveform
for the chip unprotect algorithm. The unprotection mecha-
nism begins on the falling edge of the WE pulse and is
terminated on the rising edge.
It is also possible to determine if the chip is unprotected
in the system by writing the Read Silicon ID command.
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