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| 型號(hào)： | 29F1610A |
| 廠商： | Macronix International Co., Ltd. |
| 元件分類： | EEPROM |
| 英文描述： | The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each |
| 中文描述： | 該CAT24FC02是一個(gè)2 KB的EEPROM的國內(nèi)256個(gè)8位每字舉辦的串行CMOS |
| 文件頁數(shù)： | 9/39頁 |
| 文件大?。?/td> | 669K |
| 代理商： | 29F1610A |
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9
P/N: PM0506
REV.1.7, JUN. 15, 2001
MX29F1610A
Any page to be programmed should have the page in the
erased state first, i.e. performing sector erase is
suggested before page programming can be performed.
The device is programmed on a page basis. If a
byte(word) of data within a page is to be changed, data for
the entire page can be loaded into the device. Any
byte(word) that is not loaded during the programming of
its page will be still in the erased state (i.e. FFH). Once
the bytes of a page are loaded into the device, they are
simultaneously programmed during the internal
programming period. After the first data byte(word) has
been loaded into the device, successive bytes(words)
are entered in the same manner. The time between byte
(word) loads must be less than 30us otherwise the load
period could be teminated. A6 to A19 specify the page
address, i.e., the device is page-aligned on 128 bytes(64
words)boundary. The page address must be valid during
each high to low transition of WE or CE. A-1 to A5 specify
the byte address within the page, A0 to A5 specify the
word address withih the page. The byte(word) may be
loaded in any order; sequential loading is not required. If
a high to low transition of CE or WE is not detected whithin
100us of the last low to high transition, the load period will
end and the internal programming period will start. The
Auto page program terminates when status on DQ7 is '1'
at which time the device stays at read status register
mode until the CIR contents are altered by a valid
command sequence.(Refer to table 3,6 and Figure 1,7,8)
The read or reset operation is initiated by writing the read/
reset command sequence into the command register.
Microprocessor read cycles retrieve array data from the
memory. The device remains enabled for reads until the
CIR contents are altered by a valid command sequence.
The device will automatically power-up in the read/reset
state. In this case, a command sequence is not required
to read data. Standard microprocessor read cycles will
retrieve array data. This default value ensures that no
spurious alteration of the memory content occurs during
the power transition. Refer to the AC Read
Characteristics and Waveforms for the specific timing
parameters.
The MX29F1610A is accessed like an EPROM. When CE
and OE are low and WE is high the data stored at the
memory location determined by the address pins is
asserted on the outputs. The outputs are put in the high
impedance state whenever CE or OE is high. This dual
line control gives designers flexibility in preventing bus
contention.
CE stands for the combination of CE1 and CE2 in
MX29F1610A 48-pin TSOP package. CE and stands for
CE in 44-pin SOP package.
Note that the read/reset command is not valid when
program or erase is in progress.
READ/RESET COMMAND
BYTE-WIDE LOAD/WORD-WIDE LOAD
PROGRAM
PAGE PROGRAM
To initiate Page program mode, a three-cycle command
sequence is required. There are two " unlock" write
cycles. These are followed by writing the page program
command-A0H.
Any attempt to write to the device without the three-cycle
command sequence will not start the internal Write State
Machine(WSM), no data will be written to the device.
After three-cycle command sequence is given, a
byte(word) load is performed by applying a low pulse on
the WE or CE input with CE or WE low (respectively) and
OE high. The address is latched on the falling edge of CE
or WE, whichever occurs last. The data is latched by the
first rising edge of CE or WE. Maximum of 128 bytes of
data may be loaded into each page by the same
procedure as outlined in the page program section below.
Byte(word) loads are used to enter the 128 bytes(64
words) of a page to be programmed or the software codes
for data protection. A byte load(word load) is performed
by applying a low pulse on the WE or CE input with CE or
WE low (respectively) and OE high. The address is
latched on the falling edge of CE or WE, whichever occurs
last. The data is latched by the first rising edge of CE or
WE.
Either byte-wide load or word-wide load is
determined(Byte = VIL or VIH is latched) on the falling
edge of the WE(or CE) during the 3rd command write
cycle.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 29F1610A-10 | 制造商:MCNIX 制造商全稱:Macronix International 功能描述:16M-BIT [2M x8/1M x16] CMOS SINGLE VOLTAGE FLASH EEPROM |
| 29F1610A-12 | 制造商:MCNIX 制造商全稱:Macronix International 功能描述:16M-BIT [2M x8/1M x16] CMOS SINGLE VOLTAGE FLASH EEPROM |
| 29F1610A-90 | 制造商:MCNIX 制造商全稱:Macronix International 功能描述:16M-BIT [2M x8/1M x16] CMOS SINGLE VOLTAGE FLASH EEPROM |
| 29F200 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:2 Mbit 256Kb x8 or 128Kb x16, Boot Block Single Supply Flash Memory |
| 29F200BB-70EI | 制造商:undefined 功能描述: |
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