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參數(shù)資料
| 型號(hào)： | 29K_PERIPH |
| 英文描述： | on an Am29030 Microprocessor Design Using Slow Peripherals with 29K Family Processors |
| 中文描述： | 在一個(gè)Am29030微處理器的設(shè)計(jì)中使用29K型系列處理器慢周邊 |
| 文件頁(yè)數(shù)： | 3/3頁(yè) |
| 文件大小： | 59K |
| 代理商： | 29K_PERIPH |
PID No. 18414B
3 of 3
is required for the peripheral to give a *RDY
response to the LOAD or STORE. The
periph_time
value is the number of processor cycles required for
the peripheral to process the LOAD/STORE and
remove the interrupt request.
So, using the same example from the previous two
sections, consider a system with a 3-processor-cycle
access time to the peripheral, and a peripheral that
requires two of its cycles (six processor cycles) to
process and clear the interrupt. In this case, the delay
loop implementation is the following:
msg_scc8530_tx_intr:
; reset tx interrupt.
const it1, SCC8530_CHA_CONTROL
consth it1, SCC8530_CHA_CONTROL
const it0, 0
store 0, 1, it0, it1
mfsr it0, lru
mtsr lru, it0
const it0, DELAY
jmpf it0, .
nop
.
.
{rest of handler}
.
iret
The value of DELAY is calculated as:
DELAY = int(([2+3+6]-3) / 2;
where 2 is the access time, the first 3 is the *RDY
response time, 6 is the process interrupt clear time,
the second 3 is the number of cycles to set up the
delay loop, and 2 is the number of instructions in the
loop.
For More Information
For more information, see the appropriate processor
user’s manual.
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