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參數(shù)資料
| 型號： | 3341-54 |
| 廠商： | Peregrine Semiconductor |
| 文件頁數(shù)： | 16/16頁 |
| 文件大小： | 0K |
| 描述： | IC PLL INTEGER-N 2.7GHZ 20QFN |
| 標(biāo)準(zhǔn)包裝： | 6,000 |
| 系列： | UltraCMOS™ |
| 類型： | 時鐘緩沖器/驅(qū)動器，多路復(fù)用器 |
| PLL： | 是 |
| 主要目的： | SONET/SDH，RF 儀表系統(tǒng)，無線基站 |
| 輸入： | 時鐘 |
| 輸出： | 時鐘 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:1 |
| 差分 - 輸入:輸出： | 是/無 |
| 頻率 - 最大： | 2.7GHz |
| 電源電壓： | 2.85 V ~ 3.15 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 20-QFN（4x4） |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | PE3341 |
Product Specification
PE3341
Page 9 of 17
Document No. 70-0053-05
│ www.psemi.com
2005-8 Peregrine Semiconductor Corp. All rights reserved.
Enhancement Register
The Enhancement Register is a buffered serial
shift register, loaded from the Serial Data Port. It
activates special test and operating modes in the
PLL. The bit assignments for these modes are
shown in Table 11.
The functions of these Enhancement Register bits
are shown in Table 12. A function becomes active
when its corresponding bit is set HIGH. Note that
bits 1, 2, 5, and 6 direct various data to the Dout
pin, and for valid operation no more than one
should be set HIGH simultaneously.
The Enhancement Register is buffered to prevent
inadvertent control changes during serial loading.
Data that has been loaded into the register is cap-
tured in the buffer and made available to the PLL
on the falling edge of E_WR.
A separate control line is provided to enable and
disable the Enhancement mode. Functions are
enabled by taking the ENH control line LOW.
Note: The enhancement register bit values are
unknown during power up. To avoid enabling the
enhancement mode during power up, set the ENH
pin high (“1”) until the enhancement register bit
values are programmed to a known state.
Table 12. Enhancement Register Bit Assignments
Reserved
EE Register
Output
fp output
Power
down
Counter
load
MSEL
output
fc output
Reserved
B0
B1
B2
B3
B4
B5
B6
B7
Table 13. Enhancement Register Functions
Bit Function
Description
Bit 0
Reserved
Program to 0
Bit 1
EE Register Output
Allows the contents of the EE Register to be serially shifted out Dout, LSB (B0) first.
Data is shifted on rising edge of Clock.
Bit 2
fp output
Provides the M counter output at Dout.
Bit 3
Power down
Powers down all functions except programming interface.
Bit 4
Counter load
Immediate and continuous load of counter programming.
Bit 5
MSEL output
Provides the internal dual modulus prescaler modulus select (MSEL) at Dout.
Bit 6
fc output
Provides the R counter output at Dout.
Bit 7
Reserved
Program to 0
Obsolete
Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com
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