2005-8 Peregrine Semiconductor Corp. All rights reserved. Gr" />
參數(shù)資料
型號(hào): 3342-56
廠商: Peregrine Semiconductor
文件頁(yè)數(shù): 3/16頁(yè)
文件大?。?/td> 0K
描述: IC PLL INTEGER-N 3GHZ 20QFN
標(biāo)準(zhǔn)包裝: 6,000
系列: UltraCMOS™
類型: 時(shí)鐘緩沖器/驅(qū)動(dòng)器,多路復(fù)用器
PLL:
主要目的: RF 儀表系統(tǒng),無(wú)線基站
輸入: 時(shí)鐘
輸出: 時(shí)鐘
電路數(shù): 1
比率 - 輸入:輸出: 1:1
差分 - 輸入:輸出: 是/無(wú)
頻率 - 最大: 3GHz
電源電壓: 2.85 V ~ 3.15 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 20-VFQFN 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝: 20-QFN(4x4)
包裝: 帶卷 (TR)
Product Specification
PE3342
Page 11 of 17
Document No. 70-0091-04
│ www.psemi.com
2005-8 Peregrine Semiconductor Corp. All rights reserved.
Gross EEPROM Programming Timing Grid
Figure 7 shows a gross PE3342 EEPROM
programming timing grid although each individual
step has been described thoroughly in previous
sections. It starts with EE Register load, and then
together with other parameters a Vpp_ERASE
negative pulse is applied to Vpp pin to erase the
EEPROM contents and followed by a Vpp_WRITE
pulse for EEPROM write cycle. The separation
between the Vpp_ERASE and Vpp_WRITE pulse
has to be at least 100 ms if mechanical relays are
used to avoid both being on at the same time.
After EE programming, the contents of the
EEPROM cells can be verified by setting
Enhancement Register Bit 1. A procedure shown
in Figure 8 is applied twice. The first time is to
load the EE Register from EEPROM and the
second time is to shift out the EE Register
contents through Dout pin.
Figure 7. Gross PE3342 EEPROM Programming Timing Grid
Data
S_WR
Vpp_ERASE
Vpp_WRITE
0V
3V
0V
3V
0V
12.5V
0V
-8.5V
25 ms
EE Register
load
EE PROM
Erase
EE PROM
Write
0V
40 ms
E_WR
0V
3V
EELoad
3V
EESel
0V
3V
Clock
0V
3V
Dout
0V
3V
>=100 ms
Rough time scale
The final set
of Dout is
EEPROM
content
Note: ENH/ (Pin 20) is at low (0) for this process.
EE Register
shifted out
through Dout
EE
Pro
g
ra
m
in
g
EE
v
e
ri
fy
CHANNEL
CODE
ENH code set's
Dout mux to EE
EE Register
load from
EEPROM
Obsolete
Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com
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