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參數(shù)資料
| 型號： | 33991 |
| 廠商： | Motorola, Inc. |
| 英文描述： | Gauge Driver Integrated Circuit |
| 中文描述： | 儀表驅(qū)動集成電路 |
| 文件頁數(shù)： | 13/36頁 |
| 文件大?。?/td> | 660K |
| 代理商： | 33991 |
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MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
33991
13
TIMING DESCRIPTIONS AND DIAGRAMS
Figure 4. Single 16-bit Word SPI Communication
Figure 5. Multiple 16-bit Word SPI Communication
Data Input
The Input Shift register captures data at the falling edge of
the SCLK clock. The SCLK clock pulses exactly 16 times only
inside the transmission windows (CS in a logic [0] state). By the
time the CS signal goes to logic [1] again, the contents of the
Input Shift register are transferred to the appropriate internal
register, according to the address contained in bits 15-13. The
minimum time CS should be kept high depends on the internal
clock speed. That data is specified in the SPI Interface Timing
table. It must be long enough so the internal clock is able to
capture the data from the Input Shift register and transfer it to
the internal registers.
Data Output
At the first rising edge of the SCLK clock, with the CS at logic
[0], the contents of the status word register are transferred to
the Output Shift register. The first 16 bits clocked out are the
statusbits.Ifdatacontinuestoclockinbeforethe CStransitions
to a logic [1], the device begins to shift out the data previously
clocked in FIFO after the CS first transitioned to logic [0].
COMMUNICATION MEMORY MAPS
The 33991device is capable of interfacing directly with a
microcontroller, via the 16-bit SPI protocol described and
specified below. The device is controlled by the microprocessor
and reports back status information via the SPI. This section
provides a detailed description of all registers accessible via
serial interface. The various registers control the behavior of
this device.
A message is transmitted by the master starting with the
MSB (D15) and ending with the LSB (D0). Multiple messages
can be transmitted in succession to accommodate those
applications where daisy chaining is desirable, or to confirm
transmitted data, as long as the messages are all multiples of
16 bits. Data will transfer through daisy chained devices,
illustrated in Figure 5. If an attempt is made to latch in a
message smaller than 16-bits wide, it is ignored.
The 33991uses six registers to con the device and control
the state of the four H-bridge outputs. Registers are addressed
via D15-D13 of the incoming SPI word. Refer to Table 2.
Internal registers are
loaded som etim e
C S B
S I
S C LK
D 15
D 1
D 2
D 3
D 4
D 5
D 6
D 7
D 8
D 9
D 14
D 13
D 12
D 11
D 10
O D 12
D 0
O D 13
O D 14
O D 15
O D 6
O D 7
O D 8
O D 9
O D 10
O D 11
O D 1
O D 2
O D 3
O D 4
O D 5
1.
S O is tri-stated when C S B is logic 1.
N O TE S:
O D 0
S O
O utput shift register is
loaded here
SCLK
CS
SI
SO
C S B
S I
S C LK
D 15
D 1*
D 2*
D 13*
D 14*
D 15*
D 0
D 1
D 14
D 13
D 2
D 0*
O D 13
O D 14
O D 15
D 14
D 15
O D 0
O D 1
O D 2
D 1
D 2
D 13
1.
2.
3.
4.
S O is tri-stated w hen C S B is logic 1.
D 15, D 14, D 13, ..., and D 0 refer to the first 16 bits of data into the G D IC .
D 15*, D 14*, D 13*, ... , and D 0* refer to the m ost recent entry of program data into the G D IC .
O D 15, O D 14, O D 13, ..., and O D 0 refer to the first 16 bits of fault and status data out of the G D IC .
N O TE S
:
D 0
S O
CS
SCLK
SI
SO
F
Freescale Semiconductor, Inc.
Go to: www.freescale.com
n
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 33-991 | 制造商:Ideal Industries Inc 功能描述:LTKII,350MHZ,CAT6 W/CAT6 ADPT |
| 3399-1 | 制造商:3M 功能描述:3399-1 |
| 33992 | 制造商:Ideal Industries Inc 功能描述:LTKII500MHZ,CAT6A W/CAT6A ADPT |
| 33992510000001 | 功能描述:電纜組件 CABLE KIT RoHS:否 制造商:Molex 產(chǎn)品:Power Assemblies 類型:Cable Assembly 連接器端口 A:No Connector 連接器端口 A 管腳計(jì)數(shù):4 連接器端口 B:No Connector 連接器端口 B 管腳計(jì)數(shù): 型式:Male 線規(guī) - 美國線規(guī)（AWG）:20, 28 長度:0.305 m 顏色:Black, Red |
| 33993 | 制造商:Ideal Industries Inc 功能描述:LTKII1000MHZ,CAT7A W/CAT6AADPT |
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